Analog Layout Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Melbourne, FL
Posted: 100 days ago
Freshness: Confirmed live yesterday
Nearby: 38 roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $183k

$134k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $152,875–$214,000.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Analog Layout Engineer

Role Posting Log in to save

As an Analog Layout Engineer within the Silicon Engineering Group, you will contribute to the evolution of Analog/Mixed-Signal circuits including SerDes, PLLs, and sensors for systems-on-chip. You will translate design concepts into silicon by crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits alongside circuit designers. Your daily work involves running design verification tools, managing layout tradeoffs, and interpreting LVS, DRC, and ERC reports to meet engineering specifications. The role requires expertise in deep submicron CMOS and FinFET technologies, as well as experience with ultra-high speed ADC/DAC. You will utilize Cadence Virtuoso, Cadence Innovus, and scripting languages like SKILL, Perl, TCL, Shell, or Python. Technical competencies include managing IR drop, RC delay, electromigration, self-heating, and coupling capacitance while performing custom and standard cell-based floor-planning.

Skills

Analog Layout Mixed-Signal FinFET Cadence Virtuoso Cadence Innovus SKILL Python TCL Perl Shell DRC LVS ERC DFM floor-planning PCell ADC DAC RC Delay Electromigration

What you'll do

Create sophisticated layouts for mixed-signal and analog circuits including SerDes, PLLs, and sensors.
Translate design concepts into silicon by collaborating with circuit designers to optimize performance.
Review floorplans and manage critical layout tradeoffs to meet engineering specifications.
Run complete sets of design verification tools to ensure high-quality results.
Interpret LVS, DRC, and ERC reports to identify and resolve physical verification issues.
Implement analog designs that achieve tight matching, low noise, and low power consumption.
Perform custom and standard cell-based floor-planning and hierarchical layout assembly.
Address technical challenges including IR drop, RC delay, electromigration, and coupling capacitance.

What we're looking for

Bachelor of Science degree or higher (MSEE or Ph.D. preferred) in Electrical and Computer Engineering.
Minimum of 10 years of relevant industry experience.
At least 10 years of experience in analog/mixed-signal layout design for deep submicron CMOS circuits.
At least 3 years of experience with FinFET technologies.
Proficiency in Cadence Virtuoso advanced features, Cadence Innovus, and PCell creation.
Expertise in physical verification (DRC, ERC, LVS) and technical understanding of IR drop, RC delay, and electromigration.
Programming skills in SKILL, Perl, TCL, Shell, or Python for CAD automation.
Experience with high-speed ADC/DAC, floorplanning, and hierarchical layout assembly.