Analog Layout Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 100 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $183k

$134k most similar roles pay here $228k

This listing doesn't post a salary. Most similar roles pay $152,875–$214,000.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Analog Layout Engineer

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As an Analog Layout Engineer within the Silicon Engineering Group, you will contribute to the evolution of Analog/Mixed-Signal circuits including SerDes, PLLs, and sensors for systems-on-chip. You will translate design concepts into silicon by crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits alongside designers. Your daily work involves running design verification tools, managing project schedules, and coordinating layout tradeoffs while interpreting LVS, DRC, and ERC reports to meet engineering specifications. The role requires expertise in deep submicron CMOS and FinFET technologies, with a focus on achieving tight matching and low noise. You will utilize Cadence Virtuoso, Cadence Innovus, and scripting languages like SKILL, Perl, TCL, Shell, or Python. Technical competencies include understanding IR drop, RC delay, electromigration, self-heating, and coupling capacitance for high-speed ADC/DAC components.

Skills

Analog Layout Mixed-Signal FinFET Cadence Virtuoso Cadence Innovus SKILL Python TCL Perl Shell DRC LVS ERC floor-planning PCell CAD Automation Machine Learning ADC DAC

What you'll do

Create sophisticated layouts for mixed-signal and analog circuits including SerDes, PLLs, and sensors.
Translate design concepts into silicon by collaborating with circuit designers to optimize performance.
Review floorplans and manage complex layout trade-offs for high-performance SOCs.
Run complete sets of design verification tools to ensure engineering specifications are met.
Interpret LVS, DRC, and ERC reports to identify and resolve physical verification issues.
Implement analog designs that achieve tight matching, low noise, and low power consumption.
Perform custom and standard cell-based floor-planning and hierarchical layout assembly.
Address technical challenges including IR drop, RC delay, electromigration, and coupling capacitance.

What we're looking for

Bachelor of Science degree or higher (MSEE or Ph.D. preferred) in Electrical and Computer Engineering.
Minimum of 10 years of relevant industry experience.
At least 10 years of experience in analog/mixed-signal layout design for deep submicron CMOS circuits.
At least 3 years of experience with FinFET technologies.
Proficiency in programming and scripting using SKILL, Perl, TCL, Shell, and/or Python.
Expertise in implementing analog layouts with tight matching, low noise, and low power consumption.
Proficiency in floorplanning, hierarchical layout assembly, and interpreting physical verification reports (DRC, ERC, LVS).
Experience with Cadence Virtuoso advanced features, Cadence Innovus, and CAD automation.