Analog Layout Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Waltham, MA
Salary: $157,700–$280,600 / yr
Posted: 100 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $183k

This role $219k

$126k most similar roles pay here $297k

This role pays more than 81% of similar roles. Most pay $152,875–$214,000 — the shaded band above. At the midpoint, this role pays about $219k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Analog Layout Engineer

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As an Analog Layout Engineer within the Silicon Engineering Group, you will contribute to the evolution of Analog/Mixed-Signal circuits, including SerDes, PLLs, and sensors for systems-on-chip. You will translate design concepts into silicon by crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits alongside circuit designers. Your daily work involves running design verification tools, managing project schedules, and coordinating layout tradeoffs while interpreting LVS, DRC, and ERC reports to meet engineering specifications. The role requires expertise in deep submicron CMOS and FinFET technologies, with a focus on achieving tight matching, low noise, and low power consumption. You will utilize Cadence Virtuoso, Cadence Innovus, and scripting languages like SKILL, Perl, TCL, Shell, or Python to solve complex physical verification and CAD automation challenges within the semiconductor domain.

Skills

Analog Layout Mixed-Signal FinFET Cadence Virtuoso Cadence Innovus SKILL Python TCL Perl Shell DRC LVS ERC floor-planning PCell Machine Learning CAD Automation RC Delay Electromigration

What you'll do

Create sophisticated layouts for mixed-signal and analog circuits including SerDes, PLLs, and sensors.
Review floorplans and analyze intricate circuits in collaboration with circuit designers.
Run complete sets of design verification tools to ensure layout integrity.
Interpret LVS, DRC, and ERC reports to resolve issues and meet engineering specifications.
Manage layout trade-offs while optimizing for matching, low noise, and low power consumption.
Perform custom and standard cell-based floor-planning and hierarchical layout assembly.
Address physical effects such as IR drop, RC delay, electromigration, and coupling capacitance.
Utilize Cadence Virtuoso advanced features and automation tools to complete complex designs.

What we're looking for

Bachelor of Science degree or higher (MSEE or Ph.D. preferred).
Minimum of 10 years of relevant industry experience.
At least 10 years of experience in analog/mixed-signal layout design for deep submicron CMOS circuits.
At least 3 years of experience with FinFET technologies.
Proficiency in Cadence Virtuoso advanced features, Cadence Innovus, and PCell creation.
Experience with physical verification reports including DRC, ERC, and LVS.
Programming skills in SKILL, Perl, TCL, Shell, or Python for CAD automation.
Technical knowledge of IR drop, RC delay, electromigration, self-heating, and coupling capacitance.