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Active Keyword: Wireless Design Remove filter Clear all

20 of up to 20 (filtered)

Wireless SoC Design Engineer

Apple Inc

Waltham, MA 10 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

San Diego, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
Save

Wireless SoC Design Engineer

Apple Inc

Irvine, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog Verilog ASIC Design RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Digital Design
10+ yrs exp
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Wireless SoC Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
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Wireless SoC Design Engineer

Apple Inc

San Diego, CA 10 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
Save

Wireless SoC Design Engineer

Apple Inc

Irvine, CA 10 days ago $122,700–$214,300
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog Verilog ASIC Design Flow RTL Design SoC Architecture AXI AHB UPF Low-Power Design LINT CDC RDC EDA Tools Micro-architecture Specification Digital Design
Save

Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis Microarchitecture VLSI SoC Signal Processing Bit-true Verification
10+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Signal Processing
10+ yrs exp
Save

Wireless RTL Design Engineer

Apple Inc

Irvine, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
10+ yrs exp
Save

Test Base Station Designer, Wireless Technologies & Ecosystems

Apple Inc

San Diego, CA 11 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday High trust Above market
5G NR 4G LTE C++ Python 3GPP Layer1 Layer 2 Layer 3 NAS Network Simulation Multi-threading Pre-silicon Emulation Virtual Platforms Keysight Anritsu R&S automation tool chain
5+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 12 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Design Verification front end CAD tools
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD
Save

Wireless RTL Design Engineer

Apple Inc

Irvine, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
Save

Wireless Design Verification Engineer

Apple Inc

Sunnyvale, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM ASIC Verification Mixed-Signal Co-simulation Functional Coverage Assertion-Based Verification Python PLL DAC ADC RF Digital Design Verification Planning DMS real-number-modeling
10+ yrs exp
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Wireless Design Verification Engineer

Apple Inc

San Diego, CA 17 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM ASIC Verification Mixed-Signal Co-simulation Functional Coverage Assertion-Based Verification Python PLL DAC ADC RF Digital Design Verification Planning
10+ yrs exp
Save

Wireless Design Verification Engineer

Apple Inc

Irvine, CA 17 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM ASIC Verification Mixed-Signal Co-simulation Functional Coverage Assertion-Based Verification Python PLL DAC ADC RF Digital Design Verification Planning DMS Models
10+ yrs exp
Save

Wireless Design Verification Engineer

Apple Inc

Sunnyvale, CA 17 days ago $129,300–$225,300
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM Python Verilog VHDL Mixed-Signal Verification Real-Number Modeling Assertion-Based Verification RTL Simulation Bash Perl ASIC Verification Functional Coverage Digital Design
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Wireless Design Verification Engineer

Apple Inc

San Diego, CA 17 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM Python Verilog VHDL Mixed-Signal Verification Real-Number Modeling Assertion-Based Verification RTL Simulation Bash Perl ASIC Verification Functional Coverage
Save

Test Base Station Designer, Wireless Technologies & Ecosystems

Apple Inc

San Diego, CA 21 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday High trust Above market
5G NR 4G LTE C++ Python 3GPP Layer1 Layer 2 Layer 3 NAS Network Simulation Multi-threading Pre-silicon Emulation Virtual Platforms Keysight Anritsu R&S
5+ yrs exp
Save