Wireless Design Verification Engineer

What you'll do

• Lead subsystem-level verification of Radio digital controllers and data paths from planning through closure.
• Architect UVM testbench environments and infrastructure for radio control systems and PLL controllers.
• Develop constrained random scenarios for complex radio protocols and multi-domain interactions.
• Lead digital and mixed-signal co-simulation efforts using SystemVerilog behavioral and DMS models.
• Define verification requirements and debug complex issues spanning digital and RF/analog domains.
• Establish verification strategies and best practices for radio-modeled subsystems.
• Mentor team members on radio verification approaches and technical best practices.

What we're looking for

• BS degree and a minimum of 10 years of relevant industry experience.
• Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
• Deep knowledge of ASIC verification flows with SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
• Experience developing verification environments from scratch and bringing up complex designs in simulation.
• Experience with constrained random testing, functional coverage, and assertion-based verification.
• Experience verifying Radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems (preferred).
• Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, DAC/ADCs (preferred).
• Experience with digital + mixed-signal co-simulation using SystemVerilog analog behavioral models or real-number-modeling (preferred).