Browse tech roles

FPGA Vivado Digital Signal Processing C C++ Linux DSP Algorithms RTL Development Timing Closure Resource Optimization System-Level Software integration code Epiq Solution PDK +8 more Show less

Mentor_Graphics schematic PCB_layout MathCad PSpice Saber Ethernet PCIe SerDes eFuse FET Thermal LiB DC_DC FMEA Preliminary_Hazard_Analyses embedded_software verification_and_validation high_speed_Communication_Buses Body_controls lighting_controls +16 more Show less

IEC 60601 Electronic PCB design Schematics Circuit simulation PCB Assembly Drawings Design Controls Risk Management Change Control Quality Engineering CI/CD Statistical Analysis Python PostgreSQL Git JIRA Confluence +11 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux +8 more Show less

Mentor_Graphics PCB_layout_design High_speed_Communication_Buses Ethernet PCIe SerDes Design_rule_checks Design_for_Manufacturability ECAD_library_parts Digital_analog_HW_interfaces Mentor_Graphics_schematic_and_layout Simulation_tools Component_engineering Procurement Supply_chain_teams Design_for_Assembly SI_PI_EMC_Thermal_Mechanical_expertise +12 more Show less

Mentor_Graphics_Xpedition Mentor_Graphics_ORCAD PCB_layout Circuit_design Schematic_creation Oscilloscopes Signal_generators Multimeters Power_supplies Automotive_software_architecture Automotive_electronic_hardware Semiconductor_design Electrical_Engineering Electronic_control_unit CI/CD +10 more Show less

Cadence VLSI ASIC SerDes PLL Analog to Digital converters ESD structures CMOS Sub-micron CMOS technologies +4 more Show less

Cadence CMOS PLL SerDes Analog to Digital converters ESD structures +1 more Show less

Cadence CMOS PLL SerDes Analog to Digital Converters ESD Structures Sub-micron Technology +2 more Show less

SystemVerilog UVM VMM Perl Python C C++ PCIe USB SATA Simulation Debugging CoverageDrivenVerification AssertionBasedVerification +9 more Show less

C C++ Python CUDA HIP Linux DRM/GEM ROCm IREE PyTorch Triton LLVM MLIR GPU HPC AI Compiler Performance Modeling System-Level Programming Kernel-Mode Drivers Memory Management Framework Internals Quantization Techniques Attention Mechanisms Mixture-of-Experts +20 more Show less

Cadence CMOS PLL SerDes Analog to Digital converters ESD structures Sub-micron CMOS technologies +2 more Show less

Dracula Hercules Calibre Prime-yield Mixed-signal circuit design Mask layout design Verification tools BSEE +3 more Show less

Dracula Hercules Calibre Prime-yield Mixed-signal circuit design Mask layout design Verification tools BSEE +3 more Show less

perl Python skill MASK and LAYOUT Design经验 团队合作能力 人际交往能力 积极性和正能量 +2 more Show less

perl Python scripting Layout Design Mask Design

Verilog RTL Python Perl C C++ PCI-Express CXL ASIC VLSI Digital systems Computer Architecture CMOS transistors and circuits DFT timing analysis floor-planning ECO bring-up & lab debug arbiters synchronization bus protocols interconnect networks caches +18 more Show less

Dracula Hercules Calibre Prime-yield