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Signal Integrity FPGA Xilinx Altera HDL SERDES DDR3 DDR4 DDR5 I2C JTAG UART SPI PCIe eMMC Linux Mentor Graphics DxDesigner Vivado Quartus HyperLynx Sigrity PowerSI PowerDC ADS Ansys HFSS SPICE Python Perl +22 more Show less

System Architecture Python Perl Ruby SOC Debugging Validation Scripting Logic Analyzers Oscilloscopes Hardware Modeling Software Systems Engineering +7 more Show less

SerDes Ethernet Circuit Design Schematic Creation PCB Layout Mentor Graphics Xpedition ORCAD Signal Integrity Power Integrity Root Cause Analysis Oscilloscopes Signal Generators Multimeters ECU +9 more Show less

FPGA Digital Signal Processing C C++ Vivado Linux RTL Hardware Design RF Communication Epiq Solution PDK Timing Closure Resource Optimization +7 more Show less

Verilog SystemVerilog RTL ASIC Design VLSI Python Perl Micro-architecture Digital Systems Timing Closure Logic Design Synthesis floor plan +8 more Show less

Cadence Mixed-Signal CMOS VLSI DRC LVS Python Perl SKILL Calibre Dracula Hercules Primeyield Floor Planning SerDes PLL +11 more Show less

SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug +11 more Show less