Senior Digital Design Verification Engineer, Hardware

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
156 days ago
Freshness
Confirmed live yesterday

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $177k
$126k most similar roles pay here $228k

This role pays less than 51% of similar roles. Most pay $161,500–$212,500 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Digital Design Verification Engineer, Hardware

As a Senior Digital Design Verification Engineer - Hardware, you will join the team responsible for verifying the design and implementation of cutting-edge SerDes IPs. Your daily responsibilities include verifying digital designs, golden models, and micro-architecture using advanced UVM methodologies. You will build reusable bus functional models, monitors, checkers, and scoreboards while following a coverage-driven verification methodology. The role involves defining verification scope, developing infrastructure, and executing test plans within compressed schedules to ensure design correctness. You will utilize SystemVerilog, random stimulus, functional coverage, and assertion-based verification methodologies. Additional technical skills include experience with simulation and debug tools, as well as Perl, Python, or C/C++. The work focuses on the specific domain of SerDes IPs supporting high-speed protocols for applications in gaming, artificial intelligence, deep learning, and autonomous driving.

What you'll do

  • Verify the design and implementation of SerDes IPs using advanced UVM methodologies.
  • Build reusable bus functional models, monitors, checkers, and scoreboards for coverage-driven verification.
  • Define the verification scope and develop necessary verification infrastructure for complex designs.
  • Create and implement comprehensive test plans to verify designs within compressed schedules.
  • Verify golden models and micro-architecture of high-speed SerDes IPs.
  • Perform thorough verification of digital designs at the unit, sub-system, and SoC levels.
  • Utilize SystemVerilog, random stimulus, functional coverage, and assertion-based verification methodologies.

What we're looking for

  • Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).
  • At least 5 years of validated experience in verification at the Unit, Sub-system, or SOC level.
  • Expertise in SystemVerilog is required.
  • Experience using random stimulus, functional coverage, and assertion-based verification methodologies is required.
  • Proficiency in UVM/VMM methodologies and industry standard tools for simulation and debug is required.
  • Experience with bus or interconnect protocols such as PCI Express, USB, or SATA is preferred.
  • Experience verifying complex SerDes systems, mixed-signal designs, and modeling analog circuits is preferred.
  • Proficiency in Perl, Python, or C/C++ programming languages is preferred.

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