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Active Keyword: Memory Control Design Engineer Remove filter Clear all

6 of up to 20 (filtered)

Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA
3+ yrs exp
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Lead Design Verification Engineer, Memory Controller

Amd

San Jose, CA 35 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
System Verilog UVM Formal Verification DDR5 LPDDR6 HBM4 Synopsys VCS Cadence Xcelium Assertion-Based Verification Gate-Level Simulation Power-Aware Verification VC Formal JasperGold Questa Formal Network-on-Chip Regression Management
8+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Staff Memory Controller Architecture and Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification SoC IC Package Scripting
4+ yrs exp
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Memory Control Design Engineer

Qualcomm

San Diego, CA 40 days ago $121,800–$182,600
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL DDR LPDDR PCDDR C C++ Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis x86 ARM Micro-architecture Logic Design
2+ yrs exp
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Senior RTL Design Engineer, DDR/LPDDR Memory Controller

Amd

Austin, TX +2 109 days ago $178,400–$267,600
Actively hiring Confirmed live yesterday High trust Above market
RTL Design Verilog SystemVerilog Python Perl Tcl Digital Logic Design Computer Architecture DDR LPDDR EDA Tools Lint CDC Timing Analysis Synthesis Simulation IP Microarchitecture
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