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Active Keyword: Logic Design Remove filter Clear all

9 of up to 20 (filtered)

Logic Design Engineer

Microsoft

6 days ago $102,100–$202,200
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog System Verilog RTL Logic Design Synthesis Timing Closure Lint CDC UPF Low Power Analysis Formal Equivalence Verification Power Analysis ARM Scripting VCLP Verilog Simulators
2+ yrs exp Hybrid
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Senior Logic Design Engineer

Microsoft

11 days ago $119,800–$234,700
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog System Verilog Static Timing Analysis SDC Synthesis Physical Design DFT Python Tcl Perl UPF Lint CDC Low Power Analysis Formal Equivalence Verification ARM SoC Design
5+ yrs exp Hybrid
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STA & Custom Logic Design Engineer

Apple Inc

Sunnyvale, CA 12 days ago $129,300–$225,300
Actively hiring Confirmed live today High trust Below market
STA Mixed-Signal Design SPICE Python Tcl Perl PrimeTime Tempus NanoTime SDC DFT SerDes ADC SRAM POCV Circuit Modeling RTL
3+ yrs exp
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STA & Custom Logic Design Engineer

Apple Inc

Sunnyvale, CA 12 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
STA Mixed-Signal Design SPICE Python Tcl Perl PrimeTime Tempus NanoTime SDC DFT SerDes ADC SRAM RTL Circuit Modeling POCV
10+ yrs exp
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AI/ML Logic Design Engineer-Senior

Qualcomm

Austin, TX 40 days ago $133,900–$200,900
Actively hiring Confirmed live yesterday High trust Below market
SystemVerilog RTL Design Python Perl Shell Scripting Logic Synthesis Static Timing Analysis AI/ML Git Microarchitecture Instruction Set Architecture Digital Design
2+ yrs exp
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Senior Scientist, AI/ML, Biologics Design

Gilead Sciences

Foster City, CA 54 days ago $169,320–$219,120
Actively hiring Confirmed live today High trust Competitive pay
Machine Learning Python PyTorch JAX Deep Learning Protein Language Models Generative Modeling Representation Learning Multimodal Learning Geometric Neural Networks Active Learning AlphaFold Biologics Design Protein Engineering Drug Discovery
Hybrid
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Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 67 days ago $151,000–$251,800
Actively hiring Confirmed live today Trusted Competitive pay
Verilog VHDL ASIC Design Flow RTL Design AMBA ACE AXI CHI STA DFT ECO Python Perl Logic Synthesis Timing Analysis Floor-planning Memory Controller Coherent Interconnect Cache Design On-chip Network Topologies
6+ yrs exp
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Logic Design Engineer

Amd

Santa Clara, CA 94 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
Verilog RTL ASIC Design Mixed-Signal Design High-Speed SerDes DDR GDDR HBM STA CDC UPF Power Estimation Silicon Bring-up Synthesis Digital Design Microarchitecture
Hybrid
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