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Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

San Jose, CA 21 days ago $138,000–$206,000
Actively hiring Confirmed live 2 days ago High trust Below market
Verilog SystemVerilog RTL Design UCIe PCIe CXL NoC SoC Integration IP-XACT AXI ACE CHI APB Python Tcl Perl AI/ML Agentic AI
5+ yrs exp
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