Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Interconnect IP Remove filter Clear all

6 of up to 20 (filtered)

Principal Micro-architect, Coherent Interconnect

Samsung Electronics

San Jose, CA +1 15 days ago $221,700–$364,800
Actively hiring Confirmed live today High trust Above market
RTL Design Verilog SystemVerilog ASIC Design Flow STA DFT ECO AMBA5 CHI AMBA4 ACE AXI Coherent Interconnect LLC Python Perl Computer Architecture Memory Subsystem Architecture
10+ yrs exp
Save

Principal Die-to-Die Interconnect Modeling Architect

Broadcom

San Jose, CA +1 19 days ago $167,500–$268,000
Actively hiring Confirmed live today High trust Competitive pay
MATLAB Python SystemC Verilog RTL SerDes UCIe Monte Carlo Signal Integrity Communication Theory Algorithm Verification Silicon Correlation Hardware Architecture Analog Non-idealities
10+ yrs exp
Save

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

San Jose, CA 67 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog RTL PCIe CXL UCIe SoC Microarchitecture Python Tcl Perl AXI ACE CHI APB IP-XACT NoC AI/ML Agentic AI Chiplet
5+ yrs exp
Save

Principal Design Engineer, High-Speed Interconnect

Arm Holdings

Austin, TX 99 days ago $249,900–$338,100
Actively hiring Confirmed live today High trust Above market
SystemVerilog RTL PCIe CXL UALink AXI CHI ACE APB CDC RDC Formal Verification Synthesis Timing Analysis Waveform Debug Microarchitecture Cache Hierarchies Memory Systems High-Speed I/O Chiplets
8+ yrs exp Hybrid
Save