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9 of up to 20 (filtered)

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 3 days ago Trusted Competitive pay
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging
3+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Waltham, MA 45 days ago $165,800–$292,400
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Out-of-Order Execution Branch Prediction Instruction Fetch Waveform Debugging
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Out-of-Order Execution Branch Prediction Instruction Fetch Register Renaming Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Waltham, MA 45 days ago $165,800–$292,400
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Design Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design Instruction Fetch Branch Prediction
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 45 days ago
Actively hiring Confirmed live 3 days ago Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Fetch Branch Prediction Out-of-Order Execution Register Renaming Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Santa Clara, CA 93 days ago $129,300–$194,700
Actively hiring Confirmed live 2 days ago Low trust Below market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Scheduling Memory Subsystems
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