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Senior FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, CA 9 days ago $125,000–$195,000
Actively hiring Below market
Xilinx Vivado FPGA RTL MATLAB Fixed_point_arithmetic Digital_signal_processing Multiple_clock_domain_designs High_utilization_FPGA_designs
Hybrid
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Principal FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, CA 16 days ago $175,000–$225,000
Actively hiring Competitive pay
Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems
Hybrid
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FPGA Prototyping Design Engineer

Apple Inc

Sunnyvale, CA 49 days ago $126,800–$220,900
Actively hiring Competitive pay
Verilog SystemVerilog Xilinx FPGA Vivado IP Integrator Linux Python Tcl Git PCIe I2C SPI UART High-speed SERDES IEEE 802.11 Bluetooth Synopsys HAPS Make TeamCity
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Wireless FPGA Prototype Design Engineer

Apple Inc

San Francisco, CA 52 days ago $126,800–$220,900
Actively hiring Competitive pay
FPGA Verilog Python Perl Shell C JTAG Oscilloscope Logic Analyzer LitePoint Palladium IEEE 802.11 Bluetooth APB AHB AXI USB I2C SPI
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FPGA Prototyping Design Engineer

Apple Inc

Sunnyvale, CA 74 days ago $181,100–$318,400
Actively hiring Above market
Verilog SystemVerilog Xilinx FPGA Linux CDC FPGA timing constraint I2C SPI UART ILA Vivado IP integrator SERDES PCIe IEEE 802.11 Bluetooth Synopsys HAPS Python Tcl Git Perforce TeamCity
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