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Active Keyword: FPGA Design Remove filter Clear all

8 of up to 20 (filtered)

Senior FPGA Design and Verification Engineer

ASML

Wilton, CT 2 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS
4+ yrs exp
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Staff Engineer, FPGA Design/Verification

GE Aerospace

Grand Rapids, MI +2 2 days ago
Actively hiring Confirmed live yesterday Posted this week High trust
VHDL UVM FPGA ASIC CPLD Intel Quartus Lattice Diamond Microsemi Libero Mentor Graphics Expedition PCIe AXI SERDES DMA MIL-STD-1553 DO-254 System on Chip High Speed Data Interfaces
8+ yrs exp
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Director FPGA Silicon Design Engineering

Amd

San Jose, CA 11 days ago $248,800–$373,200
Actively hiring Confirmed live yesterday High trust Above market
FPGA SoC Chiplet RTL Partial Reconfiguration Bitstream Silicon Architecture Memory Hierarchy High-Speed Interconnects Synthesis Place-and-Route System Integration Debug Observability
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SoC Systems & Infrastructure Engineer

Qualcomm

San Diego, CA 28 days ago $115,600–$173,400
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC SoC RTL Verilog SystemVerilog FPGA Emulation Python C/C++ Tcl Perl Linux Embedded Linux JTAG Git CI/CD EDA Veloce Palladium PCIe AXI I2C Ethernet
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 95 days ago $125,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA Digital Signal Processing RTL Xilinx Vivado MATLAB Logic Analyzers Hardware Verification Timing Closure Synthesis Simulation Test Bench Development MIMO
6+ yrs exp Hybrid
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Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 102 days ago $175,000–$225,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
FPGA RTL Design Xilinx Vivado Digital Signal Processing Python Perl MATLAB Logic Analyzers Timing Closure Simulation test bench development Wireless Communication Systems
10+ yrs exp Hybrid
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FPGA/ASIC Design Engineer, Silicon Engineering

SpaceX

Redmond, WA 113 days ago $125,000–$145,000
Actively hiring Confirmed live 2 days ago Low trust Below market
ASIC FPGA Verilog SystemVerilog VHDL Python C++ Bash EDA Tools VCS Questa Spyglass Xilinx Vivado Altera Quartus II AXI AHB APB DSP
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FPGA Firmware Engineer / FPGA Design Engineer

Qualcomm

San Diego, CA 123 days ago $115,600–$173,400
Actively hiring Confirmed live 2 days ago High trust Below market
FPGA System Verilog RTL HDL Xilinx Intel C++ Python Embedded Linux ARM AXI PCIe I2C LVDS Ethernet Git JIRA Agile VLSI EDA
2+ yrs exp
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