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CPU Server Physical Design Clock Engineer

Qualcomm

Austin, TX +1 2 days ago $148,300$222,500
Actively hiring Posted this week Competitive pay
SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clock_Tree_Synthesis HDL Verilog SystemVerilog Cadence Synopsys Calibre

CPU Server Physical Design Engineer

Qualcomm

Santa Clara, CA 64 days ago $167,100$250,700
Actively hiring Competitive pay
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Tensilica Instruction Extension (TIE) Linux