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C C++ Python Image Signal Processing ISP 3A Computer Architecture Embedded Systems Power Optimization Logic Design +5 more Show less

ASIC Design Firmware RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Power Management Verification Validation Scripting +6 more Show less

SystemVerilog C/C++ Python ASIC Emulation FPGA Prototyping Cadence Palladium Siemens Veloce Synopsys ZeBu RTL Verification Linux Shell Scripting SoC Architecture PCIe CXL DDR Ethernet AI-Assisted Engineering Tools +12 more Show less

Program Management Digital SoC Mixed-Signal IC RF Chips Gantt Charts Risk Mitigation Resource Forecasting Plan of Record Process Improvement +4 more Show less

SerDes SI/PI PDN Oscilloscope BERT TDR Spectrum Analyzer Python C C++ Java Linux UEFI PCIe CXL Ethernet UCIe PAM4 S-parameters +14 more Show less

Python C# Test Automation VLSI Mixed-Signal DDR LPDDR Signal Integrity Power Integrity Oscilloscopes J-BERT Silicon Debug Characterization +8 more Show less

Python Java C++ Linux VLSI DFT DFM Machine Learning Signal Integrity Oscilloscopes Spectrum Analyzers Logic Analyzers Network Analyzers Advantest 93K Teradyne UFlex +10 more Show less

SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation +12 more Show less

SystemVerilog UVM Verilog SystemVerilog Assertions ASIC SoC Formal Verification UPF AXI APB AHB DFI JEDEC DDR LPDDR HBM Constrained-Random Verification Coverage-Driven Verification Simulation Waveform Analysis +15 more Show less

IT Infrastructure Cyber Security Project Management Technical Requirements Gathering Service Delivery Proposal Development SAP Access Classified IT Information Technology Strategic Planning Infrastructure Solutions +6 more Show less