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ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

GNSS Signal Processing C++ Python Matlab Machine Learning RTL Design Fixed-point Modeling Firmware Hardware Verification AI Tools System Design Demodulation Decoding Algorithms +9 more Show less

ATE DFT Scan ATPG JTAG Memory BIST C C++ Perl JMP VLSI CMOS Analog Mixed Signal ADC DAC PLL Codecs +13 more Show less

LLMs RAG Agent Frameworks Docker Kubernetes Service Mesh CI/CD Cloud-Native Architecture GitHub Copilot Claude Code Copilot Studio Azure AI Prompt Engineering +8 more Show less

MLOps Kubernetes OpenShift Python Docker Helm GitOps Infrastructure as Code CI/CD Generative AI LLM Vector Databases Cloud Infrastructure Telemetry Distributed Systems +10 more Show less

Java Spring Java EE RESTful APIs Oracle PostgreSQL Microservices Event-driven Systems AWS Azure GCP PCF Kubernetes Docker CI/CD Infrastructure as Code Agile Scrum DevOps SDLC +15 more Show less

System Verilog UVM OVM Verilog RTL Hardware Verification Simulation Assertion Emulation Digital Design +5 more Show less

Oracle Cloud ERP SAP S/4HANA ERP SAP ECC Oracle E-Business Suite Data Migration Integration Testing Automation Scrum SAFe PMP PgMP Prosci Project Management Change Management +10 more Show less

Excel PowerPoint Jira Tableau Agile Data Analysis Macros Pivot Tables AI Tools Project Management Program Management MS Bookings +7 more Show less

RTL ASIC Design Synthesis Physical Design Synopsys Conformal LEC Synopsys Formality Synopsys PrimeTime Tcl Perl Python VLSI CMOS PPA Tape-out FINFET GAA +12 more Show less