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Active Keyword: ASIC Design Verification Engineer Remove filter Location: Santa Clara Remove filter Clear all

5 of up to 20 (filtered)

Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA +5 35 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS
8+ yrs exp Hybrid
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ASIC Design Verification Engineer

Qualcomm

Santa Clara, CA 40 days ago $113,000–$169,600
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR SOC Cache post silicon debug PASIM Power Verification
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ASIC Design Verification Engineer

Qualcomm

Santa Clara, CA 40 days ago $134,500–$201,700
Actively hiring Confirmed live today Trusted Below market
SystemVerilog UVM C++ Python Formal Verification assertion based verification UPF DDR SOC Cache post silicon debug PASIM Power Verification
2+ yrs exp
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Senior ASIC Design Verification Infrastructure and Tools Engineer, GPU

Nvidia

Remote (Santa Clara, CA) +3 75 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis
5+ yrs exp Remote
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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 92 days ago
Actively hiring Confirmed live today Trusted
System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification
5+ yrs exp Hybrid
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