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Active Keyword: ASIC Design Verification Engineer Remove filter Location: Santa Clara Remove filter Clear all

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ASIC Design Verification Engineer

Qualcomm

Santa Clara, CA 23 days ago $107,400–$161,200
Actively hiring Confirmed live 2 days ago Trusted Below market
SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR Cache SoC tape out post silicon debug PASIM Power Verification
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Senior ASIC Design Verification Infrastructure and Tools Engineer

Nvidia

Remote (Santa Clara, CA) +3 29 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics
5+ yrs exp Remote
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ASIC Design Verification Engineer

Qualcomm

Santa Clara, CA 38 days ago $107,400–$161,200
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout
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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 46 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation
5+ yrs exp Hybrid
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ASIC Design Verification Engineer

Qualcomm

Santa Clara, CA 73 days ago $126,700–$190,100
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR Cache SoC post silicon debug Power Verification PASIM Simulation
2+ yrs exp
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