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Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools +13 more Show less

TCL PERL EDA Tools RF Verification RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +7 more Show less

TCL PERL EDA Tools RTL Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout Flow and Methodology Development +6 more Show less

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Physical Design Convergence Power Integrity Analysis Custom Clock Design AI Tools +10 more Show less

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment +14 more Show less

Verilog VHDL Cadence Virtuoso Synopsys IC Compiler Calibre TritonRoute Mentor Graphics Calibre Python Perl UNIX/Linux Git SVN JIRA Confluence CI/CD +10 more Show less

Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration +13 more Show less

Python Tcl Spice static timing analysis tools inductance effects parasitic extraction performance analysis power delivery machine learning data science CAD tools scripting languages Silicon verification advanced technology nodes SoC designs +10 more Show less