R&D Engineer Physical Design

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Posted: 8 days ago
Closes: Dec 6, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $174k

This role $187k

$119k most similar roles pay here $242k

This role pays more than 61% of similar roles. Most pay $139,000–$209,750 — the shaded band above. At the midpoint, this role pays about $187k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 103 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 101 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · R&D Engineer Physical Design

Apply Now Log in to save

Join Broadcom’s Design Implementation team within the ASIC Products Division as a senior physical design engineer, where you will play a pivotal role in developing cutting-edge CMOS ASICs for AI/ML, wireless, networking, computing, and storage applications. Your responsibilities include direct customer communication, integrating various IP blocks such as memories, SerDes, and I/O subsystems, evaluating design trade-offs, addressing timing closure challenges, conducting signal integrity analysis, and managing chip-level planning through tapeout. You will work with advanced technologies like CMOS process nodes and utilize industry-standard tools for physical verification and sign-off. Ideal candidates possess a BS in Electrical Engineering with 12+ years of experience or an MS with 10+ years, along with expertise in ASIC design flows and methodologies.

Skills

Verilog VHDL Cadence Virtuoso Synopsys IC Compiler Calibre TritonRoute Mentor Graphics Calibre Python Perl UNIX/Linux Git SVN JIRA Confluence CI/CD

What you'll do

Integrate Broadcom IPs, memories, SerDes, and I/O subsystems into ASIC designs.
Evaluate design trade-offs involving power consumption, area utilization, and performance.
Address timing closure challenges to ensure signal integrity in chip designs.
Perform comprehensive timing analysis for both mission-critical and test modes.
Plan, place, and route components at the chip level for efficient physical verification.

What we're looking for

BS Degree in Electrical Engineering with 12+ years of relevant experience or MS in Electrical Engineering with 10+ years of relevant work experience.
Experience integrating Broadcom IPs, memories, SerDes, and I/O subsystems into complex ASIC designs.
Proficiency in evaluating design trade-offs involving power, area, and performance for advanced CMOS ASICs.
Expertise in addressing challenges related to timing closure and signal integrity during the physical design phase.
Hands-on experience with chip-level planning, place and route, physical verification, and tapeout processes.

Similar roles

Physical Design Engineer

Broadcom

San Jose, CA 8 days ago $141,300–$226,000

Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration

Save

Physical Design Engineer

Broadcom

San Jose, CA 8 days ago $143,800–$230,000

Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter

Save

Careers

Qualcomm

San Diego, CA 52 days ago

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PTPX ICC Calibre Sonata QCAT Qualcomm SNAP Linux Git JIRA Confluence

Save

Careers

Qualcomm

Santa Clara, CA 111 days ago

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PT PowerAware ICC/Innovus Calibre Synopsys DC Cadence Genus ModelSim/QuestaSim Linux Git JIRA Confluence

Save

Physical Design Engineer

Qualcomm

San Diego, CA 20 days ago $98,500–$147,700

Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ Tcl Unix/Linux Cadence Synopsys ModelSim Xilinx Vivado Git JIRA Confluence CI/CD

Save

Physical Design Engineer

Cisco

Remote (San Jose, CA) 5 days ago $165,000–$241,400

Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment

Remote

Save