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Active Keyword: Design Verification Engineer Remove filter Location: San Francisco Remove filter Clear all

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Design Verification Engineer

Apple Inc

San Francisco, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
SystemVerilog UVM Python Perl TCL LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation RTL Assertion Coverage Collection Waveform Viewers
10+ yrs exp
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Wireless Design Verification Engineer

Apple Inc

San Francisco, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth WLAN Zigbee UWB AMBA RTL Verification Constrained Random Testing
10+ yrs exp
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PHY Design Verification Engineer

Apple Inc

San Francisco, CA 17 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog UVM Verilog SystemVerilog Assertion Python Shell Perl Matlab FPGA Palladium Machine Learning AI RTL Verification Constrained Random Testing Functional Coverage Bluetooth UWB WLAN Zigbee
10+ yrs exp
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PHY Design Verification Engineer

Apple Inc

San Francisco, CA 79 days ago $129,300–$225,300
Actively hiring Confirmed live yesterday Low trust Competitive pay
SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium Matlab Machine Learning AI Bluetooth UWB WLAN Zigbee Constrained Random Testing
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Wireless Design Verification Engineer

Apple Inc

San Francisco, CA 79 days ago $129,300–$225,300
Actively hiring Confirmed live yesterday Low trust Competitive pay
SystemVerilog UVM Verilog Python Shell Perl Palladium FPGA RTL Verification MAC PHY DMA AMBA Bluetooth WLAN Zigbee UWB Machine Learning AI
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CAD Engineer - Design Verification Methodology

Apple Inc

San Francisco, CA 170 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
Python TCL Perl Verilog SystemVerilog VHDL Synopsys VCS Xcelium ModelSim Verdi Indago C C++ Makefile RTL Machine Learning Artificial Intelligence
3+ yrs exp
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CAD Engineer - Design Verification Methodology

Apple Inc

San Francisco, CA 171 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Low trust Above market
Python TCL Perl Verilog SystemVerilog VHDL VCS Xcelium Modelsim Cadence Synopsys Verdi Indago C C++ Machine Learning RTL
10+ yrs exp
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