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ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

Verilog SystemVerilog RTL Design DSP Formal Verification Synthesis Static Timing Analysis DFT Python Perl Hardware-Software Co-design Low-power Design Lab Bring-up Signal Processing Clock-domain Crossing +10 more Show less

Verilog SystemVerilog RTL Design DSP Digital Logic Formal Verification Synthesis Static Timing Analysis DFT Python Perl Hardware-Software Co-design Low-Power Design Lab Bring-up +9 more Show less

System Verilog HDL SIMD Logic Design Timing Analysis Synthesis Floor Planning PnR Flow Python Ruby Perl Hardware Performance Analysis +7 more Show less

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

RTL MATLAB DSP VLSI Synthesis CDC Power Analysis Fixed-point Microarchitecture Signal Processing +5 more Show less

RTL Design DSP Digital Communications UVM MATLAB FPGA Emulation Synthesis CDC RDC AXI AHB APB Fixed-point 802.11 Bluetooth 3GPP +12 more Show less