PHY RTL Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 159 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k

This role $168k

$108k most similar roles pay here $262k

This role pays less than 70% of similar roles. Most pay $168,425–$231,300 — the shaded band above. At the midpoint, this role pays about $168k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · PHY RTL Design Engineer

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The PHY RTL Design Engineer joins the wireless silicon development team to create signal processing intensive designs for wireless communication SoCs. This role involves writing specifications, defining microarchitecture based on MATLAB/C system models, and architecting area and power for low latency designs with scalability. The engineer will perform RTL coding and verification for PHY modem development, support backend activities by reviewing reports, and participate in pre- and post-silicon bringup processes. Key technical requirements include proficiency in RTL design, DSP fundamentals, digital communications knowledge, and experience with fixed-point logic. Candidates should be familiar with UVM DV environments, bit-true cycle-accurate verifications, and decoders like Viterbi, LDPC, or Polar. The role addresses the challenge of creating energy-efficient designs for wireless protocols such as IEEE 802.11, 802.15, Bluetooth, or 3GPP standards using bus fabrics like APB, AHB, and AXI.

Skills

RTL Design DSP Digital Communications UVM MATLAB FPGA Emulation Synthesis CDC RDC AXI AHB APB Fixed-point 802.11 Bluetooth 3GPP

What you'll do

Write specifications and define microarchitecture based on MATLAB/C system models.
Architect area, power, and low-latency designs with scalability and flexibility.
Develop signal processing intensive RTL logic for wireless communication SoCs.
Perform synthesis, timing constraints, and lint/CDC/RDC checks to ensure design integrity.
Conduct bit-true cycle-accurate verifications using fixed-point knowledge.
Support backend activities by reviewing reports and making necessary design adjustments.
Participate in the pre-silicon and post-silicon bringup processes.

What we're looking for

Bachelor's degree in a related field.
Understanding of DSP fundamentals and digital communications knowledge.
Proficiency in RTL design.
Familiarity with UVM DV environment and AI based efficiency improvement flows (preferred).
Strong fixed-point knowledge and experience with bit-true cycle-accurate verifications (preferred).
Knowledge of decoders, filter design, multi-radix implementation, and power management (preferred).
Experience with wireless standards, computer architecture, bus fabrics, and FPGA or emulation platforms (preferred).
Excellent communication skills and ability to work well in a team under ambitious schedules.