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Active Keyword: Digital ASIC Design Engineer Remove filter Location: San Diego Remove filter Clear all

7 of up to 20 (filtered)

High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
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Digital ASIC Design Engineer

Qualcomm

San Diego, CA 23 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday Trusted Below market
ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 30 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 37 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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ASIC Digital Design Engineer Lead

Apple Inc

San Diego, CA 42 days ago $166,600–$296,000
Actively hiring Confirmed live yesterday Trusted Above market
Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification
10+ yrs exp
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Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Low trust Below market
Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems
4+ yrs exp
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Digital ASIC Design Engineer for Mixed-Signal IPs

Qualcomm

San Diego, CA 71 days ago $115,600–$173,400
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL ASIC Design Mixed-Signal IP Digital Signal Processing VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT STA CDC Python Perl GDSII Synthesis Formal Verification Floorplanning Pre-silicon Simulation
2+ yrs exp
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