Browse tech roles

SystemVerilog UVM C++ Python Perl TCL DSP QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

SystemVerilog UVM C++ Jasper VCFormal Python Perl TCL Makefile Git CI/CD Docker AWS Kubernetes +9 more Show less

LTspice Spice TI WorkBench Cadence Allegro DxDesigner AC Power Integrity Simulation DC Power Integrity Simulation High efficiency DC-DC power conversion Phase and gain margins Power supply layout Thermal design rules Multi-phase power delivery Ultra-low noise power delivery Power-up sequencing PCB layout techniques Grounding techniques Low noise etch techniques Technical presentation skills +13 more Show less

TCL Perl Python Cadence_Innovus Synopsys_ICC2 Synopsys_Design_Complier Synopsys_Formality Cadence_Logic_Equivalence_Checker Tempus Synopsys_ICV Mentor_Calibre Static_Timing_Analysis Hierarchical_floor_planning Clock_and_power_distribution Global_signal_and_I_O_planning Physical_verification_DRC/LVS Block_level_EMIR_closure ECO_strategies RTL_to_GDSII_implementation +14 more Show less

C++ C RTOS ARM processors Perforce GIT Bugzilla JIRA Jira Crucible Python make shell programming +7 more Show less

LTSpice ADS VxDesigner Allegro PCB SiP Layout Python Power Integrity simulations optical components digital control loops DSP functions +5 more Show less

C++ C RTOS ARM Python Git Perforce JIRA Bugzilla Crucible UNIX Make Shell programming +8 more Show less

Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers +10 more Show less

Verilog SystemVerilog

C++ SystemVerilog UVM SystemC Jasper VCFormal Python Docker CI/CD Git SVN Linux Windows +8 more Show less