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Physical Design RTL GDSII Floor-planning Place and Route STA Verilog Perl Tcl LVS DRC Synthesis Power Grid EM +9 more Show less

Physical Design RTL-to-GDS Logic Synthesis place-and-route STA Power Analysis Perl TCL floor-planning Digital Circuits Memory Macros Standard Cells Deep Sub-micron Technology +8 more Show less

PnR Floorplanning Timing Closure Power Distribution Electrical Verification Netlist to GDS2 Multi-Vt Design for Yield SOC Design +4 more Show less

PnR Floorplanning Timing Closure Power Distribution Electrical Verification Netlist to GDS2 Multi-Vt Design for Yield SOC Design +4 more Show less

STA Timing Closure Physical Design Perl TCL SPICE ECO Netlist Tapeout Crosstalk OCV Circuit Modeling +7 more Show less

LVS DRC ANT HVDRC Mentor Calibre Synopsys ICV Python Perl Tcl ASIC Tapeout Layout Design RDL Padring Bump Mixed Signal Lithography +12 more Show less