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SystemVerilog UVM PCIe CXL Python Perl ASIC Design Computer Architecture RTL Waveform Debug C Functional Testing Test Plans +8 more Show less

C++ Computer Architecture PCIe CXL AXI NVLink RiscV Microcode Perl Post-Silicon Validation System Architecture Encryption +7 more Show less

RAS PCIe CXL Python C++ Perl Ruby JTAG SCAN Protocol Analyzers X86 micro architecture Post Silicon Validation MCA +8 more Show less

ARM PCIe CXL Linux Kernel UEFI EDK2 Arm Trusted Firmware (TF-A) KVM OpenBMC C C++ Python IOMMU SMMU ACPI RAS Virtualization SoC Architecture Interrupt Controller Confidential Computing +15 more Show less

PCIe Ethernet CXL UCIe NVMe PAM4 SerDes ASIC Design SR-IOV DMA IOMMU SMMU RAS BIOS UEFI SPDM TDISP UALink UEC +14 more Show less

PCIe CXL UCIe Python C/C++ Perl Linux Windows SoC Validation Post-Silicon Validation Logic Analyzers Oscilloscopes Root-Cause Analysis System Architecture +9 more Show less