PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CASanta Clara, CA
Salary: $91,520–$137,280 / yr
Employment: Intern
Posted: 27 days ago
Freshness: Confirmed live yesterday
Closes: Sep 11, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $176k

This role $114k

$76k most similar roles pay here $238k

This role pays less than 81% of similar roles. Most pay $134,125–$217,987 — the shaded band above. At the midpoint, this role pays about $114k versus about $176k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 487 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 487 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op

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The 2027 PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op joins a team focused on advanced optical transceiver and SerDes technologies. In this role, the intern will participate in silicon design and architecture modeling projects while collaborating with mentor engineers to define objectives and explore technical solutions. Day-to-day responsibilities include researching, evaluating, and proposing innovative solutions for complex design problems using analytical and simulation-based approaches, as well as documenting findings and presenting results to the engineering team. The role requires expertise in areas such as device physics, circuit design, RTL/logic design, RF design, DAC/ADC design, SerDes, DSP, CDR, PLL, or clocking circuits. Candidates will utilize CAD, AI, software development, and modeling environments to support work involving high-performance mixed-signal circuits and next-generation high-speed interconnect technologies.

Skills

SerDes Optical Transceivers Silicon Design Circuit Design RTL Logic Design Design Automation RF Design DAC ADC DSP CDR PLL Clocking Circuit Design Mixed-Signal Circuits Simulation Modeling CAD

What you'll do

Execute silicon design and architecture modeling projects specifically related to SerDes optical transceivers.
Collaborate with mentor engineers to define project objectives and identify technical solutions.
Utilize CAD, AI, software development, and modeling tools to support engineering tasks.
Research and evaluate innovative solutions for complex design and architecture problems.
Perform analytical and simulation-based approaches to validate engineering designs.
Document technical findings and summarize results throughout the internship or co-op term.
Deliver a final presentation of project outcomes to the engineering team.

What we're looking for

Must be currently pursuing a PhD degree in Electrical Engineering, Computer Science & Engineering, Mathematics, Physics, or a related technical field.
Must have completed at least two years of PhD coursework or research.
Must have coursework or hands-on research experience in areas such as device physics, circuit design, RTL/logic design, or SerDes design.
Familiarity with power-efficient and high-performance circuit design methodologies is required.
Demonstrated ability to conduct technical research and apply engineering fundamentals to solve complex problems.
Interest in advanced communication systems, optical transceivers, mixed-signal circuits, and high-speed interconnect technologies.
Experience using simulation, modeling, or design tools to analyze and validate engineering designs (preferred).