Wireless SOC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $209k
This role $242k
$131k $327k
below market most similar roles pay here above market

This role pays more than 83% of similar roles. Most pay $177,200–$241,750 — the blue band above. At the midpoint, this role pays about $242k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Wireless SOC Design Verification Engineer

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As a Senior Wireless SOC Design Verification Engineer, you will join the hardware team to own the end-to-end verification scope for the N1 wireless chip. You will partner with design teams early to shape verification plans, debug corner-case failures, and verify low-power design intent using UPF. Your daily work involves verifying the Power Management Unit, CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, and peripherals like SPI and UART. You will ensure end-to-end WiFi and Bluetooth traffic flows from the subsystem level through top-level SOC integration. Utilizing SystemVerilog, UVM, and Formal Verification, you will also explore AI-assisted verification for test generation and closure. This role addresses complex hardware challenges including boot sequencing, power-cycling, and hardware-firmware interactions for large SOC systems with embedded processor cores.

Skills

SystemVerilog UVM Formal Verification UPF ASIC PCIe AXI AHB NOC WiFi Bluetooth Post-Silicon Bring-up RTL SOC Integration SPI UART AI-assisted Verification

What you'll do

  • Develop verification plans in partnership with design teams before RTL is finalized.
  • Debug corner-case failures and develop models or proofs to ensure coverage.
  • Verify low-power design intent using UPF across assigned scopes.
  • Execute formal verification methods as required by specific project needs.
  • Make independent methodology decisions to determine the best verification approach for your area.
  • Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to top-level SOC integration.
  • Implement and optimize AI-assisted verification techniques for test generation and debugging.
  • Provide post-silicon bring-up support for projects as needed.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Proven track record of working full ASIC cycles from concept to tape-out to bring-up.
  • Expertise in SystemVerilog coding and UVM methodology.
  • Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, or AXI-based bus architecture in UVM (preferred).
  • Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC (preferred).
  • Experience with Formal Verification (preferred).
  • In-depth knowledge of low power design, UPF integration, boot-up, power-cycling, and HW/FW interaction verification (preferred).
  • Experience taping out large SOC systems with embedded processor cores (preferred).

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