Wireless SOC Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $122,700–$214,300 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $209k

This role $168k

$107k $265k

below market most similar roles pay here above market

This role pays less than 77% of similar roles. Most pay $177,200–$241,750 — the blue band above. At the midpoint, this role pays about $168k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Wireless SOC Design Verification Engineer

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JOB TITLE: Wireless SOC Design Verification Engineer As a Wireless SOC Design Verification Engineer, you will join the team responsible for the N1 wireless chip to own verification scope end-to-end. You will start by verifying specific blocks or features and gradually expand your scope toward subsystem and SOC integration. Your daily responsibilities include shaping verification plans before RTL lands, debugging corner-case failures, and verifying end-to-end WiFi and Bluetooth traffic flows. You will work on the Power Management Unit, CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, and boot sequencing. Key technical requirements include proficiency in SystemVerilog, UVM methodology, and UPF for low-power design intent. You will also utilize AI-assisted tools for test generation and verification closure while gaining exposure to formal verification and post-silicon bring-up.

Skills

SystemVerilog UVM Formal Verification UPF PCIe AXI AHB WiFi Bluetooth SOC Integration RTL Post-Silicon Bring-up Bus Fabric NOC SPI UART

What you'll do

Shape the verification plan early in the design cycle before RTL is finalized.
Debug corner-case failures and build models or proofs to catch them.
Verify low-power design intent using UPF within your assigned scope.
Verify end-to-end WiFi and Bluetooth traffic flows from subsystem to SOC integration.
Apply AI-assisted tools for test generation, debugging, and verification closure.
Perform formal verification on projects as required by the team.
Participate in post-silicon bring-up for projects reaching that stage.

What we're looking for

Minimum requirement of a bachelor's degree.
Strong academic record (GPA).
Proficiency in SystemVerilog.
Strong analytical thinking and problem-solving skills.
Familiarity with UVM methodology (preferred).
Exposure to PCIe, Bus Fabric, NOC, AHB, and AXI-based bus architectures in a UVM environment (preferred).
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC (preferred).
Experience with Formal Verification (preferred).
In-depth knowledge of low power design, UPF integration, boot-up, power-cycling, and HW/FW interaction verification (preferred).

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