Wireless Radio Verification Engineer

What you'll do

• Lead subsystem-level verification of radio digital controllers and data paths from planning through feature closure.
• Architect sophisticated UVM testbench environments and infrastructure for radio control systems and PLL controllers.
• Develop constrained random scenarios for complex radio protocols and multi-domain interactions.
• Lead digital and mixed-signal co-simulation efforts using SystemVerilog behavioral models and real-number modeling.
• Define verification requirements and debug complex issues across digital, RF, and analog domains.
• Create verification strategies for radio-modeled subsystems to ensure robust operation in diverse environments.
• Mentor team members on radio verification approaches and establish industry best practices.

What we're looking for

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Demonstrated expertise verifying complex digital ASICs with a track record of successful silicon tapeouts.
• Deep knowledge of ASIC verification flows using SystemVerilog and UVM, including testbench architecture and coverage-driven methodologies.
• Experience developing verification environments from scratch and bringing up complex designs in simulation.
• Experience with constrained random testing, functional coverage, and assertion-based verification.
• Experience verifying radio digital controllers, DSPs, PLL control systems, or wireless transceiver subsystems (preferred).
• Exposure to RF/analog system designs such as LNAs, Mixers, PLLs, amplifiers, LDOs, DACs, or ADCs (preferred).
• Experience with digital and mixed-signal co-simulation using SystemVerilog behavioral models or real-number modeling (preferred).