Wireless Radio Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $122,700–$214,300 / yr
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $168k

$111k most similar roles pay here $233k

This role pays less than 66% of similar roles. Most pay $163,037–$212,500 — the shaded band above. At the midpoint, this role pays about $168k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Wireless Radio Verification Engineer

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As a Wireless Radio Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for advanced WiFi SoCs. You will verify radio digital controllers and subsystems by developing UVM testbench environments, bus functional models, and infrastructure for complex radio control and datapath paths including PLLs, power management, and co-existence mechanisms. Your daily work involves implementing constrained random scenarios to exercise radio protocols, tracking regressions, and addressing coverage gaps while collaborating with Design, RF, and Systems teams. You will utilize SystemVerilog, Verilog or VHDL, and Python for automation and simulation. The role focuses on the technical challenge of bridging digital verification with RF and analog domains, specifically validating complex radio control sequences and operating modes to enable high-performance multi-gigabit wireless technology across various hardware components like DACs, ADCs, and amplifiers.

Skills

UVM SystemVerilog Python Verilog VHDL Mixed-Signal Verification Assertion-Based Verification RTL Simulation Functional Coverage Perl Bash RF Real-Number Modeling ASIC Verification

What you'll do

Verify radio digital controllers and subsystems from initial test planning through feature closure.
Develop UVM testbench environments, bus functional models, and infrastructure for radio control paths.
Implement constrained random scenarios to exercise radio protocols and state machine interactions.
Perform mixed-signal verification using SystemVerilog analog behavioral or real-number models.
Drive coverage closure by tracking regressions, debugging issues, and addressing gaps.
Develop Python automation scripts to support verification flows and regression infrastructure.
Define verification strategies for complex transceiver paths including PLLs, DAC/ADC data paths, and power management.

What we're looking for

Must have a minimum of a bachelor's degree.
Must understand ASIC verification flows using SystemVerilog, including UVM testbench development and RTL simulation.
Must have experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
Must have experience with digital design fundamentals in Verilog or VHDL.
Must have experience with scripting languages such as Python or similar for automation.
Preferred experience with constrained random testing, functional coverage, and assertion-based verification.
Preferred exposure to mixed-signal modeling concepts including real-number modeling.
Preferred exposure to RF/analog system design components like LNAs, Mixers, PLLs, amplifiers, LDOs, DACs, and ADCs.

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