Wireless Radio Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $178k

This role $165k

$109k most similar roles pay here $230k

This role pays less than 58% of similar roles. Most pay $156,620–$199,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $178k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless Radio Verification Engineer

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Join Apple's Wireless Connectivity team as a Wireless Radio Verification Engineer, contributing to the development of advanced WiFi SoCs that power millions of devices globally. You will ensure the success of silicon through sophisticated testbenches and verification methodologies, collaborating closely with Design, RF, PHY, and Systems teams to understand specifications and develop comprehensive test strategies for complex radio control paths including PLLs, DAC/ADC data paths, and power management. Your daily tasks include developing UVM testbench environments, implementing constrained random scenarios, and driving coverage closure while working on digital verification that bridges into the RF/analog domain using SystemVerilog and Python automation scripts. Essential skills include a deep understanding of ASIC verification flows with SystemVerilog, experience in UVM methodology, and proficiency in scripting languages like Python for automation.

Skills

SystemVerilog UVM Python Perl Bash VHDL Verilog CI/CD Git JIRA Confluence

What you'll do

Develop UVM testbench environments for radio control and datapath subsystems.
Implement constrained random scenarios to exercise complex radio protocols and sequences.
Collaborate on digital + mixed-signal verification using SystemVerilog models.
Track regressions, debug issues, and address coverage gaps in verification.
Define verification strategy with cross-functional teams including Design, RF, and Systems.

What we're looking for

Bachelor’s degree in a relevant field required.
Experience with ASIC verification flows using SystemVerilog and UVM testbench development.
Ability to develop comprehensive verification environments and debug functional issues.
Knowledge of digital design fundamentals including Verilog or VHDL.
Proficiency in Python scripting for automation and regression infrastructure.
Strong problem-solving skills and collaborative approach to engineering challenges.

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