Wireless Radio Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $178k

This role $174k

$116k most similar roles pay here $232k

This role pays more than 60% of similar roles. Most pay $156,620–$199,250 — the shaded band above. At the midpoint, this role pays about $174k versus about $178k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless Radio Verification Engineer

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Join Apple's Wireless Connectivity team as a Wireless Radio Verification Engineer, contributing to the development of advanced WiFi SoCs that power millions of devices globally. You will develop sophisticated verification environments using UVM testbenches and SystemVerilog for complex radio control and transceiver paths, including PLLs, DAC/ADC data paths, and co-existence mechanisms. Your role involves collaborating with Design, RF, PHY, and Systems teams to define comprehensive verification strategies and drive coverage closure through scenario creation and debugging. Essential skills include a strong grasp of ASIC verification flows, UVM methodology, SystemVerilog, and experience with Python for automation. This position requires expertise in digital design fundamentals and mixed-signal modeling concepts, enabling you to bridge the gap between digital and RF/analog domains.

Skills

SystemVerilog UVM Python Perl Bash VHDL Verilog CI/CD Git JIRA Confluence

What you'll do

Develop UVM testbench environments for radio control and datapath subsystems.
Implement constrained random scenarios to exercise complex radio protocols and sequences.
Collaborate on digital + mixed-signal verification using SystemVerilog models.
Track regressions, debug issues, and address coverage gaps in verification processes.
Define verification strategy with cross-functional teams including Design, RF, and Systems.

What we're looking for

Bachelor’s degree in a relevant field required.
Experience with ASIC verification flows using SystemVerilog and UVM testbench development.
Ability to develop verification environments, bring up designs in simulation, and debug functional issues.
Knowledge of digital design fundamentals including Verilog or VHDL.
Proficiency in Python scripting for automation and regression infrastructure.
Strong problem-solving skills and collaborative approach to engineering challenges.

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