Wireless Radio Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $188k

This role $177k

$118k most similar roles pay here $237k

This role pays more than 56% of similar roles. Most pay $163,037–$212,500 — the shaded band above. At the midpoint, this role pays about $177k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Wireless Radio Verification Engineer

Role Posting Log in to save

As a Wireless Radio Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for WiFi SoCs. You will be responsible for verifying radio digital controllers and subsystems by developing UVM testbench environments, bus functional models, and infrastructure for complex radio control and datapath paths including PLLs, DAC/ADC data paths, power management, and co-existence mechanisms. Your daily work involves creating constrained random scenarios to exercise radio protocols, tracking regressions, and addressing coverage gaps while collaborating with Design, RF, and Systems teams. You will utilize SystemVerilog, Verilog or VHDL, and Python for automation and simulation. The role focuses on the technical challenge of bridging digital verification with RF/analog domains to validate multi-gigabit wireless technology through sophisticated testbenches and comprehensive scenarios covering complex radio control sequences and operating modes.

Skills

UVM SystemVerilog Python Verilog VHDL Mixed-Signal Verification Assertion-Based Verification RTL Simulation Real-Number Modeling Perl Bash ASIC Verification Digital Design Functional Coverage

What you'll do

Verify radio digital controllers and subsystems from initial test planning through final feature closure.
Develop UVM testbench environments, bus functional models, and infrastructure for radio control and datapath subsystems.
Implement constrained random scenarios to exercise radio protocols, control sequences, and state machine interactions.
Perform mixed-signal verification using SystemVerilog analog behavioral or real-number models to validate radio control paths.
Drive coverage closure by tracking regressions, debugging functional issues, and addressing coverage gaps.
Develop Python automation scripts to support verification flows and regression infrastructure.

What we're looking for

A bachelor's degree is required.
Experience with ASIC verification flows using SystemVerilog, UVM testbench development, and RTL simulation.
Experience developing verification environments, bringing up designs in simulation, and debugging functional issues.
Proficiency in digital design fundamentals using Verilog or VHDL.
Experience with scripting languages such as Python, Perl, or Bash for automation.
Knowledge of constrained random testing, functional coverage implementation, and assertion-based verification.
Exposure to mixed-signal modeling concepts including real-number modeling.
Familiarity with RF/analog system design components like LNAs, Mixers, PLLs, amplifiers, LDOs, DACs, and ADCs.

Save