Wireless MAC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $169,625–$241,750 — the blue band above. At the midpoint, this role pays about $255k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Wireless MAC Design Verification Engineer

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JOB TITLE: Wireless MAC Design Verification Engineer The Wireless MAC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless MAC and its interfaces within the wireless SoC. The engineer will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable test benches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, and managing bug tracking. The role requires proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with shell, Python, and Perl scripting. Candidates must possess experience with ASIC verification flows, coverage models, and wireless protocols like Bluetooth, UWB, WLAN, or Zigbee. Additionally, the role involves using AI technologies for data mining and supporting validation via Palladium or FPGA.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA MAC PHY DMA

What you'll do

Create verification plans from specifications to achieve specific coverage targets for the MAC subsystem.
Build block and subsystem level test benches using UVM libraries and best-in-class DV methodology.
Develop and execute directed and constrained random tests to identify and debug design failures.
Create and analyze block/subsystem-level coverage models to identify and fill coverage gaps.
Use machine learning and AI technologies to identify design issues and ensure verification quality.
Support MAC subsystem validation using Palladium emulators and FPGA platforms.
Manage bug tracking and work directly with designers to drive the closure of identified issues.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine.
7+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficiency in shell, Python, and Perl scripting (preferred).
Experience using AI technologies in data mining/analysis or Palladium/FPGA validation (preferred).

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