Wireless MAC Design Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$165,800–$292,400 / yr
Posted
2 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k
This role $229k
$133k $309k
below market most similar roles pay here above market

This role pays more than 65% of similar roles. Most pay $169,625–$241,750 — the blue band above. At the midpoint, this role pays about $229k versus about $206k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · Wireless MAC Design Verification Engineer

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The Wireless MAC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless MAC and its interfaces within the wireless SoC. The engineer will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable test benches and verification environments using metric-driven methodology. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, and managing bug tracking. The role requires proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with shell, Python, and Perl scripting. Candidates must possess experience with ASIC verification flows, coverage models, and Palladium or FPGA validation. The work focuses on wireless protocols like Bluetooth, UWB, WLAN, or Zigbee to ensure high-quality, energy-efficient silicon design.

Skills

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium SystemVerilog Assertion Constrained Random Testing Functional Coverage Machine Learning Bluetooth UWB WLAN Zigbee AMBA RTL Verification

What you'll do

  • Create verification plans from specifications to achieve specific coverage targets for the MAC subsystem.
  • Build block and subsystem level test benches using UVM libraries and best-in-class DV methodology.
  • Develop and execute directed and constrained random tests to identify and debug design failures.
  • Manage bug tracking and work with designers to drive the closure of identified issues.
  • Create and analyze coverage models to identify gaps and add necessary test cases.
  • Utilize machine learning and AI technologies to identify design issues and ensure verification quality.
  • Support MAC subsystem validation using Palladium emulators and FPGA platforms.
  • Improve overall DV methodology and verification flows through continuous process refinement.

What we're looking for

  • BS degree and a minimum of 10 years of relevant industry experience.
  • Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
  • Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
  • Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine.
  • 7+ years of verification experience of wireless/wired communication block/subsystem (preferred).
  • Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
  • Proficient in shell, Python, and Perl scripting (preferred).
  • Experience using AI technologies in data mining/analysis (preferred).

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