MAC Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 2 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $206k

This role $177k

$116k $255k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $169,762–$241,750 — the blue band above. At the midpoint, this role pays about $177k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · MAC Design Verification Engineer

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JOB TITLE: MAC Design Verification Engineer The MAC Design Verification Engineer joins the wireless silicon development team to perform pre-silicon RTL verification of the wireless MAC and its interfaces within the wireless SoC. The engineer will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and verification environments using metric-driven verification. Key responsibilities include creating verification plans from specifications, building UVM libraries, executing directed and constrained random tests, and managing bug tracking. The role requires proficiency in Verilog, SystemVerilog, UVM, and SystemVerilog Assertion, along with shell, Python, and Perl scripting. Candidates should possess experience in ASIC verification flows, coverage models, and wireless protocols like Bluetooth, UWB, WLAN, or Zigbee. Additionally, the role involves using machine learning for data mining and supporting validation via Palladium or FPGA.

Skills

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA DMA MAC PHY

What you'll do

Create verification plans from specifications to achieve specific coverage targets for the MAC subsystem.
Build block and subsystem level testbenches using UVM libraries and reusable DV methodologies.
Develop and execute directed and constrained random tests to identify and debug design failures.
Manage bug tracking and work with designers to drive the closure of identified issues.
Create and analyze coverage models to identify gaps and add necessary test cases.
Utilize machine learning and AI technologies to identify design and testbench issues.
Support MAC subsystem validation using Palladium emulators and FPGA platforms.
Improve overall DV methodology and flows through continuous process refinement.

What we're looking for

Minimum requirement of a bachelor's degree.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.
Verification experience of one or more of the following: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine.
3+ years of verification experience of wireless/wired communication block/subsystem (preferred).
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee (preferred).
Proficient in shell, Python, and Perl scripting (preferred).
Experience using AI technologies in data mining/analysis or for identifying design and test bench issues (preferred).

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