VLSI CAD Engineer

What you'll do

• Optimize synthesis processes and resolve CAD tool issues for System-on-Chip (SoC) partitions.
• Use Cadence Genus and Tcl scripting to fine-tune the synthesis flow.
• Troubleshoot and debug synthesis methodologies to maintain seamless functionality within the silicon design framework.
• Validate and improve features to enhance Power, Performance, and Area (PPA) metrics.
• Conduct Synthesis and Place-and-Route (PnR) experiments to validate new design features.
• Ensure synthesized designs maintain logical equivalence with the original RTL.
• Develop Python automation scripts to streamline the synthesis workflow and reduce manual intervention.

What we're looking for

• Optimize processes and resolve CAD tool issues during the synthesis of System-on-Chip (SoC) partitions.
• Use industry-standard EDA tools such as Cadence Genus and the Tcl scripting language to fine-tune synthesis flows.
• Troubleshoot, debug, and refine synthesis methodologies to maintain functionality within the silicon design framework.
• Validate and improve features that contribute to Power, Performance, and Area (PPA) enhancements.
• Conduct Synthesis and Place-and-Route (PnR) experiments to assess and validate new design features.
• Maintain a strong understanding of Register Transfer Level (RTL) design and its impact on design metrics.
• Ensure synthesized designs maintain logical equivalence with the original RTL.
• Develop automation scripts using Python to streamline the synthesis workflow.