Technical Lead, Power Analysis and Optimization

Cisco

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$183,800–$263,600 / yr
Posted
100 days ago
Freshness
Confirmed live yesterday
Closes
Sep 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $224k
$130k most similar roles pay here $278k

This role pays more than 72% of similar roles. Most pay $153,437–$227,300 — the shaded band above. At the midpoint, this role pays about $224k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · Technical Lead, Power Analysis and Optimization

Technical Lead, Power Analysis and Optimization joins the Common Hardware Group to drive power efficiency from microarchitecture through physical implementation. This role bridges the gap between RTL design and silicon power to meet aggressive PPA targets for high-bandwidth packet switching systems. The successful candidate will evaluate microarchitectures using a first-principles approach, map network traffic patterns to identify inefficiencies, and develop comprehensive power vectors to simulate production workloads. Key responsibilities include performing power analysis, IR drop profiling, and collaborating with physical design teams to ensure RTL enhancements are physically viable. Required expertise includes RTL design, optimization, and power modeling, specifically utilizing PrimePower RTL. Preferred skills include experience with advanced FinFET process nodes, Tcl or Python scripting for automation, and high-speed packet switching architectures. The role focuses on solving complex power and performance challenges within the silicon development cycle.

What you'll do

  • Evaluate high-bandwidth packet switching microarchitecture using a first-principles approach to identify power inefficiencies.
  • Map application-level network traffic patterns to microarchitectural structures to drive power optimizations.
  • Implement RTL modifications based on application-specific traffic flow analysis beyond standard clock gating.
  • Integrate physical-aware methodologies early in the design cycle to align RTL architecture with implementation constraints.
  • Develop comprehensive power vectors to simulate production-level network switching workloads for precise analysis.
  • Perform power analysis, IR drop, and droop profiling to mitigate high-activity switching regions.
  • Partner with Physical Design teams to propose and verify RTL enhancements based on clock tree structures.
  • Conduct post-implementation analysis to ensure all physical optimizations meet defined power targets.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering with 8+ years of experience.
  • Master's degree in Electrical or Computer Engineering with 6+ years of experience.
  • PhD in Electrical or Computer Engineering with 3+ years of experience.
  • Experience in RTL design, optimization, and power modeling.
  • Experience performing power analysis using PrimePower RTL.
  • Experience mapping application-level workloads to microarchitectural features for power reduction.
  • Experience with high-speed packet switching architectures and advanced FinFET process nodes.
  • Proficiency in Tcl/Python scripting for automating power analysis and RTL optimization workflows.

More like this

Similar roles

SoC Power Analysis and Optimization Engineer

Apple Inc

Cupertino, CA 154 days ago $184,700$324,800
ASIC Power Analysis SOC Simulation Power Modeling Python Verilog System Verilog Machine Learning GenAI LLM Signal Processing Low Power Design RTL Automation
10+ yrs exp

SoC Power Analysis and Optimization Engineer

Apple Inc

Cupertino, CA 154 days ago $150,400$277,600
ASIC Power Analysis Power Optimization Verilog System Verilog Python Machine Learning GenAI LLM Signal Processing RTL Automation
3+ yrs exp

SoC Power Analysis and Optimization Engineer

Apple Inc

San Diego, CA 154 days ago $175,000$308,500
ASIC Power Analysis SOC Design Verilog System Verilog Python Machine Learning GenAI LLM Signal Processing Power Modeling Low Power Design Automation
10+ yrs exp

ASIC DFT Emulation Technical Lead

Cisco

Remote (San Jose, CA) 38 days ago $186,900$267,700
DFT Emulation Palladium Veloce Zebu Verilog System Verilog C C++ Tcl Python Perl JTAG MBIST Scan Architecture Boundary Scan UVM ATPG
8+ yrs exp Remote

Technical Lead

Pacific Life

Newport Beach, CA 56 days ago $184,680$225,720
Java RESTful APIs Microservices Git Kraken OpenL Flowable System Integration Architecture Quality Assurance Security Frameworks Back-End Development
8+ yrs exp

Senior Technical Lead

Booz Allen Hamilton

Washington, DC +1 23 days ago $112,800$257,000
Node.js TypeScript SQL PostgreSQL Redis ElasticSearch Java Java Script SharePoint XML Oracle MongoDB Solr Open AI Cloud Migration System Design JSON
10+ yrs exp