Staff SoC Integration and Performance Lead

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $233k
$139k most similar roles pay here $282k

This role pays more than 78% of similar roles. Most pay $166,425–$225,800 — the shaded band above. At the midpoint, this role pays about $233k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 48 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 47 roles with salary data.

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View all roles at Arm Holdings

At a glance

TL;DR · Staff SoC Integration and Performance Lead

The Staff SoC Integration and Performance Lead joins the System-on-Chip Performance Analysis Team to build early performance analysis platforms for future architecture exploration. This role involves leading the integration of performance-critical Arm IP into SoC-level RTL platforms, modifying components to evaluate various architectural variants, and bringing up platforms in simulation and emulation environments. The candidate will perform workload characterization, modify system-level firmware for boot flows, and debug complex hardware-software interactions across CPU, interconnects, and memory subsystems. Required expertise includes computer architecture, Verilog or SystemVerilog, and experience with RTL simulation, performance emulation, and AMBA protocols like AXI, ACE, and CHI. The role focuses on solving technical challenges in early performance analysis by identifying bottlenecks and refining architectural choices through the execution of bare-metal tests, benchmark workloads, and automated debug workflows to influence future SoC designs.

What you'll do

  • Integrate performance-critical Arm IP into SoC-level RTL platforms for early performance analysis.
  • Modify and stitch RTL components to evaluate various SoC configurations and architecture variants.
  • Bring up SoC platforms in RTL simulation and emulation environments for performance exploration.
  • Modify system-level firmware to enable boot flows, workload execution, and test-case bring-up.
  • Verify SoC functionality using bare-metal tests, benchmark workloads, and OS boot flows.
  • Debug performance issues across CPU, interconnects, memory subsystems, and other key SoC blocks.
  • Collaborate with architects to define and refine future SoC architecture choices.
  • Drive the resolution of integration, firmware, and workload issues across multi-disciplinary teams.

What we're looking for

  • Strong understanding of computer architecture, SoC architecture, memory subsystems, and bus/interconnect protocols.
  • Hands-on experience integrating IP and bringing up full-chip SoC test cases in RTL simulation and/or emulation environments.
  • Experience developing or modifying RTL using Verilog or SystemVerilog.
  • Experience with SoC-level debug including reset, clock, memory map, interrupt, interconnect, and firmware interactions.
  • Experience enabling workloads, benchmarks, or bare-metal tests on RTL simulation and performance emulation platforms.
  • Ability to analyze performance data and identify bottlenecks across SoC components.
  • Proficiency with Unix/Linux environments, scripting languages, and source-control systems like Git or Subversion (preferred).
  • Familiarity with Arm architecture, AMBA protocols, boot firmware, and system-level performance analysis (preferred).

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