Staff Engineer, RTL Memory Centric Computing

Samsung Semiconductor

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $208k
$152k most similar roles pay here $264k

This role pays more than 62% of similar roles. Most pay $177,800–$223,700 — the shaded band above. At the midpoint, this role pays about $208k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

Most-posted roles

View all roles at Samsung Semiconductor

At a glance

TL;DR · Staff Engineer, RTL Memory Centric Computing

Apply Now Log in to save

Join our AGICL lab as a Senior Engineer specializing in RTL Memory Centric Computing, where you will develop and optimize IP for memory-centric computing systems using Verilog, SystemVerilog, and HLS. Your daily tasks include collaborating with verification engineers to design test plans, making informed design decisions across performance, power, thermal, and cost trade-offs, and troubleshooting hardware issues. You’ll need a strong background in microarchitecture and computer architecture, along with 5+ years of experience in front-end RTL development for complex IPs like memory controllers and interconnects. Ideal candidates also have expertise in AI/ML workloads and stay current with advancements in machine learning and hardware architecture.

Skills

Verilog SystemVerilog HLS Python CI/CD PostgreSQL Kubernetes Docker AWS Grafana Prometheus Terraform

What you'll do

  • Develop IP for memory-centric computing systems using Verilog and SystemVerilog.
  • Optimize hardware designs for performance, power efficiency, and area constraints.
  • Design test plans in collaboration with verification engineers to ensure quality.
  • Make informed design decisions considering trade-offs between performance and cost.
  • Troubleshoot and debug hardware issues during the development process.

What we're looking for

  • 10+ years of industry experience with a Bachelor’s degree or equivalent
  • Strong background in microarchitecture and computer architecture
  • 5+ years of front-end design methodology involving RTL development for complex IPs
  • Experience designing Memory Controller, NOC, Interconnect IP, and Memory Centric computing IP
  • Expertise in Verilog, System Verilog, HLS, and optimizing designs for performance, power, and area
  • Troubleshoot hardware issues and collaborate with verification engineers on test plans

Related searches

More Staff Engineer jobs Staff Engineer jobs in San Jose All jobs at Samsung Semiconductor

More like this

Similar roles

Staff Engineer, RTL Design

Samsung Semiconductor

San Jose, CA today $163,000–$253,000
Verilog Synopsys Cadence MentorGraphics FPGA PCIe CXL NVMe AXI DDR4 DDR5 Ethernet Linux Windows Python Simulation Testbench CI/CD
Save

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA 21 days ago $142,200–$213,400
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools
Save

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 27 days ago $127,200–$190,800
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design
Save

Senior Engineer, RTL Design

Samsung Semiconductor

San Jose, CA today $138,000–$206,000
Verilog Synopsys Cadence MentorGraphics PCIe CXL NVMe AXI DDR4 DDR5 Ethernet FPGA Linux Windows Python Simulation TestBench CI/CD
Save

CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 14 days ago $167,100–$250,700
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Questa TCL SV CI/CD
Save