Senior SI/PI Engineer, Serdes, Satellites

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Palo Alto, CA
Salary: $115,000–$155,000 / yr
Posted: 63 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $168k

This role $135k

$105k most similar roles pay here $207k

This role pays less than 81% of similar roles. Most pay $137,500–$197,500 — the shaded band above. At the midpoint, this role pays about $135k versus about $168k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior SI/PI Engineer, Serdes, Satellites

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Sr. SI/PI Engineer - Serdes, Satellites (Starlink) joins the Payload Engineering team to provide signal and power integrity ownership for hardware enabling satellite connectivity. This role involves managing the entire product lifecycle, including IP evaluation in silicon architecture, package performance evaluation, stackup material selection, and PCB layout oversight. The engineer will design, simulate, and troubleshoot advanced satellite hardware components such as wireline and electro-optical communication systems with 10 to 112+ Gbps SERDES, high-bandwidth memory interfaces like DDR4 and LPDDR5, and power delivery networks for ASICs. Key technical requirements include proficiency in 3D EM simulation tools like CST, HFSS, or ADS, along with programming skills in Python, C, and C++. The role addresses complex hardware challenges at the intersection of electrical, mechanical, thermal, and RF engineering to ensure robust satellite performance.

Skills

Power Integrity SERDES PDN CST HFSS ADS Python C++ DDR4 LPDDR5 GPDDR6 ASIC FPGA EMI/EMC High-Speed Digital Design Transmission Line Theory

What you'll do

Design, simulate, and verify SI and PI for high-speed SERDES, memory interfaces, and power delivery networks.
Define design, analysis, and verification processes and tools for the Starlink hardware development team.
Perform early-stage evaluation of silicon architecture, package performance, and PCB material selection.
Optimize transition structures and component selections for complex power delivery networks (PDN).
Root cause and resolve issues related to manufacturing, testing, and satellite integration.
Establish best practices for simulation workflows, test methodologies, and lab equipment requirements.
Provide technical leadership and knowledge sharing on SI/PI topics across the broader engineering program.

What we're looking for

Bachelor's degree in electrical engineering, computer engineering, or physics.
5+ years of industry experience designing circuits, electronic products, or hardware.
2+ years of experience using 3D EM simulation tools and high-speed digital channel simulators like CST, HFSS, or ADS.
2+ years of research or industry experience with high-speed digital design or power integrity.
Experience designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoCs, or ASICs.
Proficiency in programming languages such as Python, C, or C++.
Ability to work in a cross-functional environment to resolve EMI/EMC issues and optimize hardware components.
Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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