below marketmost similar roles pay hereabove market
This role pays less than
80%
of similar roles. Most pay
$137,500–$197,500
— the blue band above.
At the midpoint, this role pays about
$135k
versus about
$168k
for comparable roles.
Based on 240 similar postings.
Employer
About SpaceX
SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.
SpaceX currently has
851 open roles
on FindRole.
Listed pay typically runs
$130,000–$165,000
across 590 roles with salary data.
The Sr. SI/PI Engineer - Serdes, Satellites (Starlink) joins the Payload Engineering team to provide signal and power integrity ownership for hardware enabling broadband internet connectivity. This role involves the full life-cycle development of satellite hardware, including IP evaluation, package performance, stackup material selection, and PCB layout oversight. You will specify, simulate, and troubleshoot wireline and electro-optical communication systems with 10 to 112+ Gbps SERDES, DSPs, and high-bandwidth memory interfaces like DDR4 and LPDDR5. Key responsibilities include designing power delivery networks for ASICs and defining simulation workflows. Required expertise includes 3D EM simulation tools like CST, HFSS, or ADS, along with high-speed digital design experience. You will solve complex electromagnetic and power delivery challenges across the die bump to die bump channel.
Specify, design, simulate, and verify SI and PI aspects of advanced satellite hardware.
Architect and optimize high-speed wireline communication systems and memory interfaces.
Design and optimize power delivery networks (PDNs) for complex ASICs and processors.
Derive top-level specifications for PCB materials and channel subcomponents.
Root cause and fix hardware issues found in PCB manufacturing, PCBA test, or satellite integration.
Define simulation workflows, test methodologies, and signoff criteria for the Starlink program.
Perform IP evaluation, package performance evaluation, and stackup material characterization.
What we're looking for
Bachelor’s degree in electrical engineering, computer engineering, or physics.
5+ years of industry experience designing circuits, electronic products, or hardware.
2+ years of experience using 3D EM simulation tools and high-speed digital channel simulators like CST, HFSS, or ADS.
2+ years of research or industry experience with high-speed digital design or power integrity.
Master’s degree or PhD in electrical engineering or computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity (preferred).
5+ years of experience designing hardware from concept through production with an emphasis on full life-cycle development (preferred).
5+ years of experience architecting, implementing, and debugging cutting-edge DSP based SERDES products (preferred).
U.S. citizen, national, lawful permanent resident, refugee, or asylee eligible for Department of State authorization.
Signal Integrity
SERDES
DDR4
LPDDR5
GPDDR6
QSPI NOR
eMMC
Python
C
C++
CST
HFSS
ADS
PCB Layout
EMI/EMC
DSP
Wireline Transceivers
High-Speed Digital Design
3D EM Simulation
Signal Integrity
SERDES
DDR4
LPDDR5
GPDDR6
QSPI NOR
eMMC
CST
HFSS
ADS
Python
C
C++
PCB Layout
EMI/EMC
DSP
Wireline Transceivers
High-Speed Digital Design
3D EM Simulation
Mixed-Signal ASIC
PAM4 SerDes
RF Front End
PCB Layout
Power Integrity
FPGA
Ethernet
DDR4
LPDDR5
I2C
SPI
Python
C/C++
Hardware Bring-up
Schematic Capture
space grade hardware
digital to analog converters
PCB Layout
Schematic Capture
FPGA
Python
C/C++
Ethernet
DDR4
I2C
SPI
RF Engineering
Power Electronics
Hardware Bring-up
Digital to Analog Converters
High-Speed Digital Communications
SerDes
Space Lasers
Avionics