Senior Signal Integrity Engineer, Serdes, Satellites

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Palo Alto, CA
Salary: $115,000–$155,000 / yr
Posted: 63 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $168k

This role $135k

$106k most similar roles pay here $203k

This role pays less than 82% of similar roles. Most pay $142,500–$193,500 — the shaded band above. At the midpoint, this role pays about $135k versus about $168k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

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At a glance

TL;DR · Senior Signal Integrity Engineer, Serdes, Satellites

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Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink) joins the Payload Engineering team to provide signal and power integrity ownership across the entire hardware lifecycle for satellite connectivity systems. This role involves designing, simulating, and troubleshooting advanced satellite hardware including wireline and electro-optical communication systems with high-speed SERDES, DSPs, retimers, and optoelectronics. The engineer will also manage high-bandwidth memory interfaces like DDR4 and LPDDR5, while developing power delivery networks for ASICs. Key responsibilities include defining design processes, selecting PCB materials, and optimizing transition structures from die bump to die bump. Candidates should possess expertise in 3D EM simulation tools such as CST, HFSS, or ADS, along with proficiency in Python or C/C++. The role addresses the technical challenges of high-speed digital design and power integrity within complex satellite payload hardware.

Skills

Power Integrity CST HFSS ADS Python C++ PDN SERDES DDR4 LPDDR5 GPDDR6 ASIC FPGA EMI/EMC High-Speed Digital Design Transmission Line Theory

What you'll do

Design, simulate, and verify SI and PI aspects for high-speed wireline and electro-optical communication systems.
Manage power delivery networks (PDN) and component selection for ASICs, FPGAs, and SoCs with complex requirements.
Evaluate package performance, stackup materials, and transition structures from die bump to die bump.
Root cause and resolve issues related to PCB manufacturing, assembly testing, and satellite integration.
Define standard simulation workflows, test methodologies, and signoff criteria for the Starlink program.
Develop technical specifications for high-bandwidth memory interfaces such as DDR4, LPDDR5, and GPDDR6.
Provide subject matter expertise to guide cross-functional teams in hardware architecture and signal integrity.

What we're looking for

Bachelor's degree in electrical engineering, computer engineering, or physics.
5+ years of industry experience designing circuits, electronic products, or hardware.
2+ years of experience using 3D EM simulation tools and high-speed digital channel simulators like CST, HFSS, or ADS.
2+ years of research or industry experience with high-speed digital design or power integrity.
Master's degree or PhD in electrical engineering or computer engineering with focus on electromagnetic theory or power integrity.
5+ years of experience designing and debugging cutting edge DSP based SERDES products, high-bandwidth memory interfaces, and power delivery networks.
Proficiency in programming languages such as Python, C, or C++.
Must be a U.S. citizen, permanent resident, or eligible for required export control authorizations.

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