below marketmost similar roles pay hereabove market
This role pays less than
81%
of similar roles. Most pay
$137,500–$200,000
— the blue band above.
At the midpoint, this role pays about
$135k
versus about
$169k
for comparable roles.
Based on 240 similar postings.
Employer
About SpaceX
SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.
SpaceX currently has
851 open roles
on FindRole.
Listed pay typically runs
$130,000–$165,000
across 590 roles with salary data.
Signal Integrity Engineer - Serdes, Satellites (Starlink) joins the Payload Engineering team to provide signal integrity ownership for hardware enabling Starlink broadband connectivity. You will manage the full hardware life-cycle, performing IP evaluation during silicon architecture, package performance evaluation, stack-up material selection, and PCB layout oversight. Daily responsibilities include specifying, simulating, verifying, and troubleshooting advanced satellite hardware, specifically wireline and electro-optical communication systems with 10 to 112+ Gbps SERDES, DSPs, retimers, and optoelectronics. You will also work with high-speed memory interfaces like DDR4 and LPDDR5. Required skills include 3D EM simulation tools such as CST, HFSS, or ADS, and high-speed digital channel simulators. You must solve complex technical problems involving transition structures from die bump to die bump and EMI/EMC de-sense issues.
Specify, design, simulate, and verify signal integrity for advanced satellite hardware and high-speed memory interfaces.
Perform package performance evaluations, stack-up material selection, and PCB layout oversight.
Design and optimize transition structures for channels from die bump to die bump.
Root cause and fix issues found in PCB manufacturing, PCBA testing, or satellite integration.
Derive top-level specifications for PCB materials and channel subcomponents.
Define best practices, simulation workflows, and test methodologies for all signal integrity needs.
Troubleshoot wireline and electro-optical communication systems using cutting-edge SERDES and DSPs.
What we're looking for
Bachelor’s degree in electrical engineering, computer engineering, or physics.
1+ years of industry experience designing circuits, electronic products, or hardware.
1+ years of experience using 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS, etc.).
1+ years of research or industry experience with high-speed digital design.
Master’s degree or PhD in electrical engineering or computer engineering with emphasis in electromagnetic theory, transmission line theory, or wireline transceivers (preferred).
3+ years of electronic product experience designing hardware from concept through production (preferred).
3+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (preferred).
3+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces (preferred).
U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for required Department of State authorizations.
Signal Integrity
SERDES
DDR4
LPDDR5
GPDDR6
QSPI NOR
eMMC
CST
HFSS
ADS
Python
C
C++
PCB Layout
EMI/EMC
DSP
Wireline Transceivers
High-Speed Digital Design
3D EM Simulation
mixed-signal ASIC
PAM4 SerDes
FPGA
Python
C
C++
PCB Layout
RF Front End
Power Integrity
DDR4
LPDDR5
I2C
SPI
Ethernet
Hardware Bring-up
Schematic Capture
Failure Analysis
space grade hardware
Phased Array Antennas
power conversion
PCB Layout
Schematic Capture
FPGA
Python
C/C++
Ethernet
DDR4
I2C
SPI
RF Engineering
Power Electronics
Hardware Bring-up
Digital to Analog Converters
High-Speed Digital Communications
SerDes
Space Lasers
Avionics