Senior Principal Engineer - CAD, SoC Floorplan and Advance Technode

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Diego, CA
Salary
$308,600–$417,500 / yr
Posted
1 day ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $213k
This role $363k
$135k most similar roles pay here $448k

This role pays more than 99% of similar roles. Most pay $185,000–$241,550 — the shaded band above. At the midpoint, this role pays about $363k versus about $213k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 106 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 106 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Senior Principal Engineer - CAD, SoC Floorplan and Advance Technode

Sr Principal Engineer - CAD, SoC Floorplan and Advance Technode joins the solutions engineering team to develop and optimize end-to-end methodologies for advanced silicon and multi-die system solutions. The role involves driving technology optimization for PPA on sub-2nm and future process nodes, specifically focusing on floorplan, IP, Tech, PG, and signoff convergence. Key responsibilities include developing SoC and core floorplan methodologies for hierarchical and multi-die implementations, translating foundry and DTCO capabilities into production strategies for libraries, memories, routing resources, power delivery, and clocking. The position requires expertise in low-power methodologies, UPF-based implementation, and chip finishing. Candidates must possess strong programming skills in Python and C, experience with EDA tools, Git, and distributed compute environments. This role addresses the technical challenges of advanced-node integration and 2.5D/3D products through scalable automation and AI-assisted methodologies.

What does a Engineer earn in California?

Median $209800 from 89 postings across 25 companies.

See salary data

What you'll do

  • Drive technology optimization for PPA on sub-2nm and future process nodes.
  • Develop and optimize SoC and core floorplan methodologies for hierarchical and multi-die implementations.
  • Translate foundry and DTCO capabilities into production implementation strategies for libraries, memories, and routing resources.
  • Build scalable automation and AI-assisted methodologies for technology exploration and PPA optimization.
  • Establish reference methodologies for advanced-node and 2.5D/3D products with cross-functional teams.
  • Implement low-power methodologies, UPF-based implementation, and chip finishing flows.
  • Lead technical initiatives across multi-functional groups to achieve product goals.

What we're looking for

  • Expertise in advanced-node technology and implementation is required.
  • Experience with hierarchical SoC floorplan, feedthrough, and integration is required.
  • Proficiency with low-power methodologies, UPF-based implementation, chip finishing, and sign-off flows is required.
  • Strong programming and scripting skills in Python, C, EDA tools, Git, and distributed compute environments are required.
  • Proven ability to lead technical initiatives across multi-functional groups and partner with architecture, foundry, and ecosystem partners.
  • Excellent analytical, problem-solving, communication, and teamwork skills are required.
  • Familiarity with AI-assisted build automation and large-scale PPA exploration (preferred).

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