Senior Formal Verification Engineer

Amazon Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TXSunnyvale, CARedmond, WASan Diego, CA
Salary
$185,200–$250,000 / yr
Posted
61 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $174k
This role $218k
$131k $263k
below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $161,500–$187,250 — the blue band above. At the midpoint, this role pays about $218k versus about $174k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 643 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 636 roles with salary data.

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At a glance

TL;DR · Senior Formal Verification Engineer

The Sr. Formal Verification Engineer joins the Leo Silicon Team to drive formal verification efforts for next-generation modem SoCs used in broadband communication satellites. In this role, you will apply rigorous mathematical methods to prove design correctness and uncover corner-case bugs across NOC, interconnect, modem IPs, and control logic. You will develop formal verification strategies, write and debug SystemVerilog Assertions, and build reusable infrastructure including constraint libraries and automated regression flows. Key technologies include JasperGold, Questa Formal, SystemVerilog, UVM, and AI-centric verification methodologies. You will also perform property checking, connectivity checking, register verification, and sequential equivalence checking. By collaborating with RTL designers and architects, you will use abstraction techniques and assume-guarantee reasoning to improve silicon quality and shift verification left for complex modem designs.

What you'll do

  • Develop and execute formal verification strategies using JasperGold and Questa Formal for property, connectivity, and register verification.
  • Write, review, and debug SystemVerilog Assertions (SVA) to verify complex modem SoC design behaviors.
  • Drive proof convergence by applying abstraction techniques, complexity reduction, and assume-guarantee reasoning.
  • Develop reusable formal verification infrastructure, including constraint libraries and automated regression flows in CI/CD pipelines.
  • Identify and pursue formal verification opportunities for new design blocks to champion a formal-first strategy.
  • Mentor DV engineers on formal verification techniques, SVA best practices, and proof convergence strategies.
  • Partner with EDA vendors to evaluate new formal verification capabilities and drive tool improvements.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or equivalent.
  • 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification.
  • Experience with JasperGold and/or Questa Formal.
  • Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification.
  • Experience with formal verification applications including FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
  • Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques.
  • Proficiency in SystemVerilog and UVM concepts.
  • Export control laws and regulations, candidates.

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