CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Actively hiring
Santa Clara, CA · Austin, TX Posted 24 days ago $167,100–$250,700 / year
View original post Log in to save

At a glance

AI generated

TL;DR

Join Qualcomm Technologies, Inc. as a Senior CPU Micro-architecture and RTL Design Engineer, collaborating with chip architects to develop high-performance, low-power devices based on the RISC-V architecture. Your daily tasks will include performance exploration, microarchitecture development, and specification refinement, alongside owning the RTL design process from initial concept through delivery. You’ll support functional and performance verification while working closely with a multi-functional engineering team to ensure timing, area, reliability, and testability goals are met. Ideal candidates possess expertise in microprocessor architecture components such as instruction fetch and decode, branch prediction, and cache subsystems, along with proficiency in Verilog or VHDL, logic design principles, and scripting languages like Perl or Python. This role demands a deep understanding of low power and high-performance techniques within CPU microarchitecture.

Skills

Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques

What you'll do

  • Develop and refine RTL design to meet power, performance, area, and timing goals.
  • Conduct microarchitecture development from high-level exploration to detailed specification.
  • Support functional verification of the RTL design to ensure accuracy.
  • Collaborate on performance verification to confirm RTL meets performance targets.
  • Implement physical design aspects with a multi-functional engineering team.

What we're looking for

  • Extensive knowledge of RISC-V architecture and microprocessor design.
  • Expertise in CPU microarchitecture components like branch prediction and out-of-order execution.
  • Proficiency in Verilog/VHDL for RTL development and simulation.
  • Understanding of low power and high-performance techniques in CPU design.
  • Experience with scripting languages (Perl, Python) for automation tasks.
  • Strong background in logic design principles and their timing/power implications.

Market check

Salary context

This $167,100–$250,700 range sits above 66% of similar postings on FindRole.

Peer median band

$152,200–$241,400

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$162,400–$226,587

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 564 open roles on FindRole.

Listed pay typically runs $148,300–$224,400 across 531 roles with salary data.

Most-posted roles

View all roles at Qualcomm

More like this

Similar roles

CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm

Austin, Tx,Us, US 76 days ago $148,300–$250,700
Verilog VHDL Perl Python Waveform debugging tools Simulators Instruction fetch and decode Branch prediction Instruction scheduling Register renaming Out-of-order execution Integer execution Floating point execution Load/store execution Prefetching Cache subsystems Memory subsystems Logic design principles Timing analysis Power analysis Low power techniques High performance techniques

RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, Ca,Us, US 18 days ago $142,200–$213,400
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools

Processor Micro Architect RTL Design Engineer (Multiple Levels)

Qualcomm

San Diego, Ca,Us, US 24 days ago $180,400–$270,600
Verilog System Verilog RTL digital design logic design cache memory coherency bus interface multi-core microprocessor architecture low power design functional verification static timing analysis formal verification PLDRC clock domain crossing

CPU RTL Methodology Engineer

Qualcomm

Santa Clara, Ca,Us, US 56 days ago $198,700–$298,100
Python Git Verilog SystemVerilog TCL Perl Bash CI/CD CAD RTL

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, Ca,Us, US 24 days ago $127,200–$190,800
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design

CPU Verification Engineer (RISC-V)

Qualcomm

Santa Clara, Ca,Us, US 25 days ago $167,100–$250,700
RISC-V Cache Coherence Memory ordering and Consistency Prefetching Branch Prediction Rename Speculative execution Address Translation Memory Management Random Instruction Sequencing Testbenches Transactors Assembly code Verification Methodologies Simulators Coverage collection Gate-level Simulation Waveform viewers Mixed signal Verification