SoC Power Modeling Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$184,700–$324,800 / yr
Posted
15 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $207k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $171,875–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · SoC Power Modeling Engineer

As part of the Silicon Engineering group, the SoC Power Modeling Engineer will model power dissipation and delivery for various IPs, including AI/ML accelerators, CPUs, graphics, and memory caches. The role involves establishing voltage-frequency operating points for DVFM states, modeling power for specific customer use-cases, and collaborating with architecture, thermals, PMIC, and system design teams to optimize leading-edge chips for power efficiency. This position requires correlating models to hardware data by partnering with lab, silicon characterization, and technology teams. Key technical requirements include expertise in low-power digital design, electrical properties of on-die PDN, power gating, and thermal control loops. The ideal candidate possesses skills in scripting, data analysis, and EDA tools, while maintaining a deep understanding of VLSI design flow, CMOS technology, and physical design tools for power optimization.

What you'll do

  • Model power dissipation and power delivery for various SoC IPs including AI/ML accelerators, CPUs, and graphics.
  • Establish voltage-frequency operating points for DVFM states across multiple system components.
  • Model power dissipation specifically tailored to various customer use-cases.
  • Determine peak current requirements and power rail specifications for upcoming generations of SoCs.
  • Partner with lab and test teams to correlate power models with actual hardware data.
  • Collaborate with technology, validation, and product engineering teams to establish pre- and post-silicon design points.
  • Model thermal control loops and throttling mechanisms to optimize power efficiency.

What we're looking for

  • A bachelor's degree in a relevant field.
  • Minimum of 10 years of relevant industry experience.
  • 3+ years of relevant experience, programming skills, and understanding of low-power digital design and power fundamentals (preferred).
  • Understanding of SoC power modeling, current demand, and electrical properties of on-die PDN, power gating, and system power delivery (preferred).
  • Skills in scripting, data analysis, and experience with EDA tools (preferred).
  • Understanding of VLSI design flow and CMOS technology (preferred).
  • Extensive background in EE (preferred).
  • Ability to model thermal control loops, throttling mechanisms, and use physical design tools for power optimization (preferred).

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