SoC Power Modeling Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$142,300–$263,300 / yr
Posted
15 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $207k
This role $203k
$128k most similar roles pay here $279k

This role pays less than 57% of similar roles. Most pay $171,875–$241,750 — the shaded band above. At the midpoint, this role pays about $203k versus about $207k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · SoC Power Modeling Engineer

As part of the Silicon Engineering group, the SoC Power Modeling Engineer will model power dissipation and delivery for various IPs including AI/ML accelerators, CPUs, Graphics, and memory systems. The role involves establishing voltage-frequency operating points for DVFM states, modeling power for specific customer use-cases, and collaborating with architecture, thermals, PMIC, and system design teams to optimize leading-edge chips for power efficiency. Key responsibilities include correlating models to hardware data in partnership with lab and silicon characterization teams. The ideal candidate possesses an extensive background in electrical engineering, knowledge of VLSI design flow, CMOS technology, and on-die PDN properties. Required skills include scripting, data analysis, and experience with EDA tools. This role addresses the technical challenge of modeling power profiles and thermal control loops for mobile SoC designs.

What you'll do

  • Model power dissipation and power delivery for various IPs including AI/ML, CPUs, and graphics.
  • Establish voltage-frequency operating points for DVFM states across multiple SoC components.
  • Model power dissipation specifically tailored to customer use-cases.
  • Determine peak current requirements and power rail specifications for upcoming SoC generations.
  • Collaborate with hardware teams to establish voltage-frequency design points pre- and post-silicon.
  • Correlate power models with physical hardware data from the lab and silicon characterization teams.
  • Model thermal control loops and throttling mechanisms for power optimization.

What we're looking for

  • A bachelor's degree in a relevant field and at least 3 years of relevant industry experience are required.
  • Experience with programming, low-power digital design, and power fundamentals (preferred).
  • Understanding of SoC power modeling, current demand, and electrical properties of on-die PDN, power gating, and system power delivery (preferred).
  • Skills in scripting, data analysis, and experience with EDA tools (preferred).
  • Understanding of VLSI design flow and CMOS technology (preferred).
  • Extensive background in Electrical Engineering (preferred).
  • Ability to understand and model thermal control loops and throttling mechanisms (preferred).
  • Familiarity with physical design tools for power optimization (preferred).

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