SoC Power Modeling Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$150,400–$277,600 / yr
Posted
15 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $207k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 60% of similar roles. Most pay $171,875–$241,750 — the shaded band above. At the midpoint, this role pays about $214k versus about $207k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · SoC Power Modeling Engineer

As part of the Silicon Engineering group, the SoC Power Modeling Engineer will model power dissipation and delivery for various IPs, including AI/ML accelerators, CPUs, graphics, and memory caches. The role involves establishing voltage-frequency operating points for DVFM states, modeling power for specific customer use-cases, and collaborating with architecture, thermals, PMIC, and system design teams to optimize leading-edge chips for power efficiency. You will partner with lab and silicon characterization teams to correlate models with hardware data. Required skills include an understanding of low-power digital design, on-die PDN electrical properties, power gating, and thermal control loops. The candidate should possess proficiency in scripting, data analysis, and EDA tools while demonstrating a strong background in VLSI design flow, CMOS technology, and physical design tools for power optimization within the mobile SoC domain.

What you'll do

  • Model power dissipation and power delivery for various IPs including AI/ML, CPUs, and graphics.
  • Establish voltage-frequency operating points for DVFM states across multiple SoC components.
  • Model power dissipation specifically tailored to customer use-cases.
  • Determine peak current requirements and power rail specifications for upcoming SoC generations.
  • Collaborate with hardware teams to establish pre- and post-silicon voltage-frequency design points.
  • Correlate power models with actual hardware data from the lab and silicon characterization teams.
  • Model thermal control loops and throttling mechanisms for power optimization.

What we're looking for

  • A bachelor's degree in a relevant field.
  • A minimum of 3 years of relevant industry experience.
  • Programming skills and an understanding of low-power digital design and power fundamentals (preferred).
  • Understanding of SoC power modeling, current demand, and electrical properties of on-die PDN (preferred).
  • Skills in scripting, data analysis, and experience with EDA tools (preferred).
  • Understanding of VLSI design flow and CMOS technology (preferred).
  • Extensive background in Electrical Engineering (preferred).
  • Ability to model thermal control loops, throttling mechanisms, and use physical design tools for power optimization (preferred).

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