This role pays more than
76%
of similar roles. Most pay
$177,250–$241,750
— the shaded band above.
At the midpoint, this role pays about
$242k
versus about
$210k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3553 open roles
on FindRole.
Listed pay typically runs
$165,800–$277,600
across 2740 roles with salary data.
As an SoC Physical Design Engineer, PnR, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the design cycle and manage the full netlist to GDS2 implementation while meeting specific schedule goals. Your daily responsibilities include timing, physical, and electrical verification, as well as driving signoff closure and optimizing partitions for Power, Performance, and Area. You will resolve flow issues and navigate complexities such as multi-vt strategies, multiple voltage and clock domains, and mixed signal block integration. Required expertise includes floorplanning, clock and power distribution, and experience with large SOC designs exceeding 20M gates at frequencies over 1GHz using industry standard tools.
Execute full netlist to GDS2 implementation for complex SoC partitions.
Drive physical design aspects early in the cycle by collaborating with logic design teams.
Perform timing, physical, and electrical verification to achieve signoff closure.
Optimize PnR partitions to achieve best Power, Performance, and Area (PPA).
Resolve and improve design and flow issues related to physical design.
Manage floorplanning, clock distribution, and power distribution for large SoC designs.
Address process-related issues including Design for Yield, Manufacturability, and multi-vt strategies.
What we're looking for
Minimum BS degree and 10+ years of relevant industry experience.
Experience with partition level P&R implementation including floorplanning, clock/power distribution, timing closure, and physical/electrical verification.
Experience with physical design construction and analysis flows and methodology.
MS in Electrical, Electronics, Computer Engineering, or a related field (preferred).
Experience with large SOC designs exceeding 20M gates with frequencies over 1GHz (preferred).
Familiarity with process-related issues including Design for Yield, Manufacturability, and multi-vt strategies (preferred).
Experience with industry standard tools, their capabilities, and underlying algorithms (preferred).
Experience with typical SOC issues like multiple voltage/clock domains and mixed signal integration (preferred).