SoC Physical Design Engineer, STA/Timing

Apple Inc

Confirmed live yesterday Low trust

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Work type: On-site
Location: Beaverton, OR
Posted: 40 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

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TL;DR · SoC Physical Design Engineer, STA/Timing

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The SoC Physical Design Engineer, STA/Timing will join the Physical Design team to manage the physical implementation of design partitions from netlist to tapeout for a highly complex SoC using state of the art process technology. The role involves working with design teams to debug constraints, facilitate logic changes to improve timing, and create timing ECOs for project tapeout. Key responsibilities include performing deep analysis of timing paths, implementing timing infrastructure, and creating scripts and methodologies for analysis runs. Candidates must possess strong programming skills in TCL, with additional experience in Perl or Python. Required competencies include large design STA, timing closure, and knowledge of noise, crosstalk, OCV, and circuit modeling including SPICE simulation and worst-case timing corner selection for high-performance SoC designs in sub-micron technologies.

Skills

STA Timing Closure TCL Python Perl Physical Design ECO SPICE OCV Crosstalk Circuit Modeling Netlist to Tapeout SoC Design

What you'll do

Execute the physical implementation of design partitions from netlist to tapeout.
Perform deep analysis of timing paths to identify and resolve key issues.
Create and maintain scripts and methodologies for analysis and design runs.
Develop timing ECOs to ensure successful project tapeout.
Implement timing infrastructure for complex SoC designs.
Debug design constraints and facilitate logic changes to improve timing.
Create technical documentation, guidelines, and specifications for the design process.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Strong programming skills with TCL.
Experience with large design STA and/or Timing Closure (preferred).
Experience with timing of large high-performance SoC designs in sub-micron technologies (preferred).
Deep understanding of noise, crosstalk, OCV and other timing modeling effects (preferred).
Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation (preferred).
Experience in ECO techniques and implementation (preferred).
Experience with other scripting languages such as Perl or Python (preferred).

SoC Physical Design Engineer, STA/Timing

Apple Inc

Austin, TX 40 days ago

STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout

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