SoC DFT Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Similar $210k
$143k most similar roles pay here $279k

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · SoC DFT Engineer

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As an SoC DFT Engineer within the Silicon Technologies group, you will be responsible for the complete design and manufacturing of high-performance, power-efficient system-on-chip processors. Your daily responsibilities include developing and implementing DFT architecture and infrastructure, generating structural test vectors to improve coverage, and collaborating with designers on STA, physical, power, and logical issues. You will also work with verification teams to validate implementations through simulation and coordinate with test engineers to bring up vectors on silicon. The role requires expertise in Verilog or VHDL, waveform debugging tools, and industry standards such as ATPG, JTAG, and MBIST. Additionally, you will manage STA constraints for DFT modes, perform SDF simulations, and utilize scripting to analyze ATE data during the silicon debug phase of the semiconductor design process.

Skills

DFT ATPG JTAG MBIST Verilog VHDL STA SDF Silicon Debug ATE Scripting Design Verification Waveform Debugging Compressed ATPG

What you'll do

  • Develop and implement DFT architecture and infrastructure for SoC designs.
  • Verify DFT implementations and execute engineering change orders (ECOs) with the DV team.
  • Generate structural test vectors and analyze/improve coverage metrics.
  • Resolve STA, physical, power, and logical issues in coordination with design teams.
  • Collaborate with test engineers to bring up test vectors on silicon.
  • Debug Compressed ATPG patterns, MBIST, and JTAG/1500 related issues.
  • Develop and analyze STA constraints for DFT modes and SDF simulations.
  • Analyze ATE data using scripting to support efficient silicon debug experiments.

What we're looking for

  • Bachelor of Science degree with at least 10 years of relevant industry experience.
  • Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST, and trade-offs between test quality and time (preferred).
  • Experience developing DFT specifications and driving architecture and methods for designs (preferred).
  • Knowledge of Verilog and/or VHDL, along with experience using simulators and waveform debugging tools (preferred).
  • Knowledge of industry standards for DFT and design tools (preferred).
  • Proven understanding of design verification methodologies for validating DFT implementation in simulation pre-silicon (preferred).
  • Experience debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues (preferred).
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations (preferred).

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